View TMXA846221BL-21_6961924.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

hardware design guide, revision 6 april 5, 2005 tmxa84622 ultramapper ? full transport 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 1 introduction the last issue of this data sheet was july 14, 2004 - revision 5. a change history is included in section 13 change history, on page 67 . red change bars have been installed on all text, figures, and tables that were added or changed. all changes to the text are highlighted in red. changes within figures, and the figure title itself, are highlighted in red, if feasible. formatting or gra mmatical changes have not been highlighted. deleted sections, para graphs, figures, or tables will be specifically mentioned. the documentation package for the tmxa84622 ultramapper full transport 622/155 mbit s/s sonet/sdh x ds3/e3/ds2/ ds1/e1 system chip consists of the following documents: ? the register description and the system design guide. these documents are available on a password-protected web- site. ? the ultramapper full transport product description and the ultramapper full transport hardware design guide (this document). these documents are available on the public website shown below. if the reader displays this document using acrobat reader ? , clicking on any blue text will brin g the reader to that reference point. to access related documents, including the documents mentione d above, please go to the following public website, or con- tact your agere representative (see the last page of this document). http://www.agere.com/enterpr ise_metro_access/index.html this document describes the hardware in terfaces to the agere systems tmxa84622 ultramapper full transport device. information relevant to the use of the device in a board design is covered. pin descriptions, dc electrical characteristics, timing diagrams, ac timing parameters, pack aging, and operating conditions are included. figure 1-1. ultramapper full transport block diagram and high-level interface definition (x3) m13 mux tmux sts-12/ stm-4/ sts-3/ stm-1 frm (x3) x28/x21 ds1/j1/e1 (x3) x28/x21 vtmpr mrxc ds1/j1/e1 vt/ tu ds2/ e2 ds3/ e3 tpg/tpm x3 x28/x21 ds1/e1 dja cdr spempr (x3) (0-2) cdr mcdr stspp mpu jtag lopoh x6 ds3/e3 dja (x3) e13 mux spempr (x3) (3-5) (x3) s t s - 1 l t 3 1 s t s x c system interfaces transport modes 4 ds1/j1/e1 (x86): x84/x63 + prot. 4 ds2/e2 (x86): x63/x36 + prot. (x6) ds3/e3 (x3) sts-1 (x3) nsmi (x3) sts-1 (total of 3 sts-1 max) low-speed i/o 622 mb/sts-12/stm-4 155 mb/sts-3/stm-1 clock and data lopoh 622/155 mbits/s sonet/sdh adm front end ds3/e3/ds2/ds1/e1 pdh tributary termination toac mpu if poac jtag if 66 e2, vc12 ds3xclk, e3xclk ds2, vc11 ais clocks ds1xclk, e1xclk power and gnd pins not shown 12 49 5 6 sts-3/stm-1 mate interconnect high-speed if (x3) 8 clock/sync 6 protection link 622 mb/sts-12/stm-4 155 mb/sts-3/stm-1 clock and data 8 42 24 344 3 1 1 1 2 2 10/10/02 full transport miscellaneous 24 cg pll if 5
table of contents contents page 2 agere systems inc. tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 1 introduction ................................................................................................................. .......................................................1 2 pin information .............................................................................................................. .....................................................6 2.1 ball diagram .............................................................................................................. ..................................................6 2.2 package pin assignments ................................................................................................... ........................................7 2.3 pin assignment matrix ..................................................................................................... ..........................................17 2.4 pin types ................................................................................................................. ..................................................20 2.5 pin definitions ........................................................................................................... .................................................21 3 operating conditions and reliability ......................................................................................... .......................................35 3.1 absolute maximum ratings .................................................................................................. .....................................35 3.2 recommended operating conditions ................ .......................................................................... .............................35 3.3 handling precautions ...................................................................................................... ..........................................35 3.4 thermal parameters (definitions and values) . .............................................................................. ............................36 3.5 reliability ............................................................................................................... ....................................................37 3.6 recommended powerup sequence .............................................................................................. ............................37 3.7 power consumption ......................................................................................................... .........................................37 4 electrical characteristics ................................................................................................... ..............................................39 4.1 lvcmos interface characteristics .......................................................................................... ..................................39 4.2 lvds interface characteristics ............................................................................................ .....................................40 5 timing ....................................................................................................................... .......................................................41 5.1 tmux high-speed interface timing .......................................................................................... ................................41 5.2 thssync characte ristics ........... ................ ................ ................. ................ ............. .......... ......................................42 5.3 sts-3/stm-1 mate interconnect timing ...................................................................................... .............................44 5.4 toac, poac, and lopoh timing .............................................................................................. .............................45 5.5 ds3/e3/sts-1 timing ....................................................................................................... ........................................46 5.6 nsmi timing ............................................................................................................... ...............................................47 5.7 shared low-speed line timing .............................................................................................. ..................................50 6 reference clocks ............................................................................................................. ...............................................51 7 microprocessor interface timing .................... .......................................................................... .......................................56 7.1 synchronous write mode .................................................................................................... ......................................56 7.2 synchronous read mode ..................................................................................................... .....................................58 7.3 asynchronous write mode ................................................................................................... .....................................59 7.4 asynchronous read mode .................................................................................................... ....................................61 8 other timing ................................................................................................................. ...................................................63 9 hardware design f ile references .............................................................................................. .....................................63 10 909-pin pbgam1t diagram ..................................................................................................... .....................................64 11 ordering inform ation ........................................................................................................ ..............................................65 12 glossary .................................................................................................................... .....................................................66 13 change history .............................................................................................................. .................................................67 13.1 changes to this document since revision 5 ................................................................................ .........................67 13.2 navigating through an adobe acrobat document ............................................................................. ....................67
tables of contents (continued) tables page agere systems inc. 3 hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 table 2-1. package pin assignments............................................................................................. ........................................7 table 2-2. pin matrix .......................................................................................................... ..................................................17 table 2-3. pin types ........................................................................................................... .................................................20 table 2-4. tmux block, high-speed interface i/o. ............................................................................... ...............................21 table 2-5. tmux block, protection link i/o..... ................................................................................ ....................................21 table 2-6. tmux block, clock and sync i/o...................................................................................... ..................................22 table 2-7. sts cross-connect (stsxc) block, sts-3/stm-1 mate interconne ct ...................................................... .......23 table 2-8. multirate cross-connect (mrxc) block, toac input and output channels.. .............................................. ......23 table 2-9. multirate cross-connect (mrxc) block, poac input and output channels................................................ ......24 table 2-10. ds3/e3/sts-1 out .... ............................................................................................... .........................................24 table 2-11. ds3/e3/sts-1 in.... ................................................................................................ ...........................................24 table 2-12. nsmi/sts-1 in ....... ............................................................................................... ............................................25 table 2-13. nsmi/sts-1 out .... ................................................................................................. ..........................................26 table 2-14. shared low-speed line in........................................................................................... .....................................27 table 2-15. shared low-speed line out .......................................................................................... ...................................28 table 2-16. reference clocks ................................................................................................... ...........................................29 table 2-17. low-or der path overhead access, transmit direction ................................................................. ...................29 table 2-18. low-or der path overhead access, receive direction .................................................................. ...................29 table 2-19. clock generato r .................................................................................................... ............................................30 table 2-20. microprocessor interface........................................................................................... ........................................31 table 2-21. boundary scan (ieee ? 1149.1) ....................................................................................................................... .32 table 2-22. general-purpose interface ............... ........................................................................... ......................................32 table 2-23. cdr interface...................................................................................................... ..............................................32 table 2-24. analog power and ground signals .................................................................................... ...............................33 table 2-25. digital power and ground signals ................................................................................... .................................34 table 2-26. no connects........................................................................................................ ..............................................34 table 3-1. absolute maximum ra tings............................................................................................ .....................................35 table 3-2. recommended operating conditions .................................................................................... .............................35 table 3-3. esd tolerance ....................................................................................................... .............................................35 table 3-4. thermal parameter va lues ............................................................................................ .....................................36 table 3-5. reliability data .................................................................................................... ................................................37 table 3-6. moisture sensitivity level.......................................................................................... ..........................................37 table 3-7. typical power consumption by applicatio n ............................................................................ ............................37 table 3-8. typical power consumption per block ..... ............................................................................ ..............................38 table 4-1. lvcmos input specifications ............ ............................................................................. ....................................39 table 4-2. lvcmos output specifications ........................................................................................ ..................................39 table 4-3. lvcmos bidirectional specifications ... .............................................................................. ................................39 table 4-4. lvds interface dc characteristics ................................................................................... ...................................40 table 5-1. high-speed interface input specifications ........................................................................... ...............................41 table 5-2. protection link input specifications ................................................................................ ....................................42 table 5-3. high-speed interface output specificat ions .......................................................................... .............................42 table 5-4. protection link output specifications............................................................................... ...................................42 table 5-5. sts-3/stm-1 mate interconnect input specifications .................................................................. ......................44 table 5-6. sts-3/stm-1 mate interconnect output specifications................................................................. .....................44 table 5-7. toac, poac, and lopoh input specifications .......................................................................... ......................45 table 5-8. toac, poac, and lopoh output specifications......................................................................... .....................45 table 5-9. ds3/e3 input specifications......................................................................................... .......................................46 table 5-10. sts-1 input specifications ............... .......................................................................... .......................................46 table 5-11. ds3/e3/sts-1 output specifications................................................................................. ...............................46 table 5-12. nsmi input specifications .......................................................................................... .......................................49 table 5-13. nsmi output specif ications ......................................................................................... .....................................49 table 5-14. shared low-speed line ti ming input specifications.................................................................. ......................50 table 5-15. shared low-speed line ti ming output specifications ................................................................. ....................50 table 6-1. high-speed interface input clocks specif ications .................................................................... ..........................51 table 6-2. protection link input clock specificat ions .......................................................................... ................................51
tables of contents (continued) tables page 4 agere systems inc. tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 table 6-3. ds3/e3/sts-1 input clocks specificatio ns............................................................................ .............................51 table 6-4. ds1/e1 dja input clocks specifications .............................................................................. ..............................51 table 6-5. m13/e13 input clocks specifications ................................................................................. .................................52 table 6-6. ds3/e3 dja input clocks specifications .............................................................................. ..............................52 table 6-7. lopoh input clock specifications.................................................................................... ..................................52 table 6-8. microproce ssor interface input clocks specifications.. .............................................................. .........................52 table 6-9. pll input clock specifications..................................................................................... ......................................52 table 6-10. high-speed interface output clocks specifications.................................................................. ........................52 table 6-11. protection link output clocks specifications....................................................................... .............................52 table 6-12. line timing interface output clocks specif ications ................................................................. .........................53 table 6-13. toac output clocks specifications.... .............................................................................. ................................53 table 6-14. poac output clocks specifications .................................................................................. ...............................53 table 6-15. ds3/e3/sts-1 output clocks specifications .......................................................................... ..........................54 table 6-16. lopoh output clock specifications.................................................................................. ...............................54 table 6-17. pll output clocks specifications .................................................................................. ..................................54 table 6-18. shared low-speed receive line input/output clocks specifications ................................................... ...........54 table 6-19. shared low-speed transmit line input/output clocks specifications .................................................. ...........54 table 6-20. nsmi input/output clocks specifications ............................................................................ ..............................55 table 7-1. microproce ssor interface synchronous write cycle specifications ..................................................... ...............57 table 7-2. microproce ssor interface synchronous read cycle specifications ...................................................... ..............58 table 7-3. microproce ssor interface asynchronous wr ite cycle specifications .................................................... ..............60 table 7-4. microproce ssor interface asynchronous read cycle spec ifications ..................................................... .............62 table 8-1. general-purpos e input specifications................................................................................ .................................63 table 8-2. miscellaneous ou tput specifications................................................................................. ..................................63 table 8-3. general-purpos e output specifications ............................................................................... ...............................63 table 11-1. ordering info rmation ............................................................................................... ..........................................65 table 13-1. document changes.......................... ......................................................................... ........................................67
table of contents (continued) figures page agere systems inc. 5 hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 figure 1-1. ultramapper full transport block diagram and high-lev el interface definition....................................... ...........1 figure 2-1. ultramapper full transp ort package diagram (top view) .............................................................. ....................6 figure 5-1. tmux lvds signal rise/fall timing... ............................................................................... ...............................41 figure 5-2. tmux lvds clock an d data timing .................................................................................... .............................41 figure 5-3. thssync timing diagram (mpu_master_slave = 1)...................................................................... ..........42 figure 5-4. thssync timing diagram (mpu_master_slave = 0)...................................................................... ..........43 figure 5-5. thssync timing diagram for synchronized vts ........................................................................ ....................43 figure 5-6. relationship between thssync and thsd ............. ................ ............. ............. ............. .......... ......................43 figure 5-7. sts-3/stm-1 mate rise/fall timing .................................................................................. ...............................44 figure 5-8. sts-3/stm-1 mate clock and data timing............................................................................. ..........................44 figure 5-9. toac, poac timing .................................................................................................. .......................................45 figure 5-10. lopoh timing...................................................................................................... ...........................................45 figure 5-11. ds3/e3 interface diagr am in m13/e13 block ......................................................................... .........................46 figure 5-12. nsmi clock and data timing for the sts-1 mode ..................................................................... .....................47 figure 5-13. nsmi clock and data dia gram for spempr nsmi mode.................................................................. .............47 figure 5-14. nsmi clock and data diagram for m13 nsmi mode (nsmi <---> m13 <- --> ds3 external i/o).....................48 figure 5-15. nsmi clock and data diagram for e13 nsmi mode 1 (nsmi <---> e13 <---> e3 external i/o)......................48 figure 5-16. nsmi clock and da ta diagram for e13 nsmi mode 2 (nsmi <- -> e13 <--> spempr <- -> stm-n) .............49 figure 5-17. shared low-speed line clock and data timing ....................................................................... ......................50 figure 7-1. microprocessor interfac e synchronous write cycle?mpmode pin = 1 .................................................... ......56 figure 7-2. microprocessor interfac e synchronous read cycle?mpmode pin = 1 ..................................................... .....58 figure 7-3. microprocessor interfac e asynchronous write cycle?mpmode pin = 0 ................................................... .....59 figure 7-4. microprocessor interfac e asynchronous read cycle?mpmode pin = 0 .................................................... ....61 figure 10-1. ultramapper full transp ort 909-pin pbgam1t balls and dimensions ................................................... ........64
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 6 6 agere systems inc. 2 pin information 2.1 ball diagram the tmxa84622 ultramapper full transport is housed in a 909-pin plastic ball grid array. figure 2-1 shows the ball assign- ment viewed from the top of the package. the pins are spaced on a 1.0 mm pitch. figure 2-1. ultramapper full transport package diagram (top view) t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10 12 14 16 2 34 523 25 7 31 29 15 21 3 27 11 17 913 1 33
hardware design guide, revision 6 tmxa84622 ultramapper full transport march 7, 2005 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 7 2.2 package pin assignments table 2-1. package pin assignments signal name pin addr[0] k6 addr[1] h4 addr[2] g3 addr[3] j8 addr[4] j4 addr[5] k5 addr[6] f1 addr[7] g2 addr[8] l6 addr[9] l5 addr[10] h2 addr[11] m6 addr[12] k4 addr[13] l8 addr[14] m5 addr[15] n6 addr[16] j1 addr[17] l3 addr[18] m4 addr[19] p8 addr[20] n5 adsn f3 aps_intn y1 bypass am13 cg_pllclkout af26 clkin_pll af27 csn g7 ctaprh af8 ctaprp ag10 ctapth ag9 ctaptl ag14 data[0] k1 data[1] l2 data[2] u2 data[3] n4 data[4] r8 data[5] m2 data[6] t5 data[7] m1 data[8] r5 data[9] u5 data[10] p4 data[11] n2 data[12] r4 data[13] t4 data[14] u9 data[15] p1 ds1xclk ap21 ds2aisclk v8 ds3datainclk[1] ab1 ds3datainclk[2] v4 ds3datainclk[3] v3 ds3datainclk[4] ae1 ds3datainclk[5] af1 ds3datainclk[6] ab4 ds3dataoutclk[1] ab5 ds3dataoutclk[2] ab8 ds3dataoutclk[3] ac5 ds3dataoutclk[4] ad5 ds3dataoutclk[5] ae5 ds3dataoutclk[6] ag4 ds3negdatain[1] v1 ds3negdatain[2] ac1 ds3negdatain[3] y4 ds3negdatain[4] ac2 ds3negdatain[5] y5 ds3negdatain[6] aa5 ds3negdataout[1] ac3 ds3negdataout[2] ac4 ds3negdataout[3] aj1 ds3negdataout[4] al1 ds3negdataout[5] ag3 ds3negdataout[6] aj2 ds3posdatain[1] w3 ds3posdatain[2] ab2 ds3posdatain[3] ad1 ds3posdatain[4] v5 ds3posdatain[5] w8 ds3posdatain[6] w5 ds3posdataout[1] v2 ds3posdataout[2] aa6 ds3posdataout[3] ah1 ds3posdataout[4] ak1 ds3posdataout[5] ag2 ds3posdataout[6] af4 ds3rxclkout[1] ad2 ds3rxclkout[2] ad3 ds3rxclkout[3] ab6 ds3rxclkout[4] ac8 ds3rxclkout[5] ad6 table 2-1. package pin assignments (continued) signal name pin
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 8 8 agere systems inc. ds3rxclkout[6] ae8 ds3xclk e19 dsn j5 dtn t3 e1xclk am18 e2aisclk aa1 e3xclk h18 ecsel al14 etoggle ap15 exdnup ap16 hp_intn u8 ic3staten al20 iddq al21 linerxclk[1] a18 linerxclk[2] c17 linerxclk[3] e16 linerxclk[4] c16 linerxclk[5] b16 linerxclk[6] a15 linerxclk[7] a14 linerxclk[8] c13 linerxclk[9] b13 linerxclk[10] d12 linerxclk[11] b12 linerxclk[12] d11 linerxclk[13] b11 linerxclk[14] e12 linerxclk[15] d10 linerxclk[16] h12 linerxclk[17] d9 linerxclk[18] c8 linerxclk[19] h11 linerxclk[20] b7 linerxclk[21] e9 linerxclk[22] e10 linerxclk[23] d7 linerxclk[24] e8 linerxclk[25] f9 linerxclk[26] e7 linerxclk[27] d6 linerxclk[28] g8 linerxclk[29] b4 linerxclk[30] f7 linerxclk[31] j9 linerxclk[32] f4 linerxclk[33] c1 linerxclk[34] h9 table 2-1. package pin assignments (continued) signal name pin linerxclk[35] e5 linerxclk[36] f6 linerxclk[37] a10 linerxclk[38] a12 linerxclk[39] h14 linerxclk[40] d14 linerxclk[41] a16 linerxclk[42] e17 linerxclk[43] b18 linerxclk[44] d19 linerxclk[45] h20 linerxclk[46] d21 linerxclk[47] b24 linerxclk[48] f22 linerxclk[49] b28 linerxclk[50] a29 linerxclk[51] h24 linerxclk[52] a32 linerxclk[53] d29 linerxclk[54] d30 linerxclk[55] h26 linerxclk[56] e30 linerxclk[57] f29 linerxclk[58] l30 linerxclk[59] m27 linerxclk[60] m30 linerxclk[61] n29 linerxclk[62] m31 linerxclk[63] n30 linerxclk[64] l33 linerxclk[65] n31 linerxclk[66] p29 linerxclk[67] m34 linerxclk[68] n34 linerxclk[69] t27 linerxclk[70] t33 linerxclk[71] u33 linerxclk[72] v30 linerxclk[73] w34 linerxclk[74] w31 linerxclk[75] aa34 linerxclk[76] y30 linerxclk[77] ac33 linerxclk[78] ah3 linerxclk[79] ah2 linerxclk[80] ae4 linerxclk[81] ad4 table 2-1. package pin assignments (continued) signal name pin
hardware design guide, revision 6 tmxa84622 ultramapper full transport march 7, 2005 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 9 linerxclk[82] y8 linerxclk[83] aa4 linerxclk[84] w4 linerxclk[85] u1 linerxclk[86] t2 linerxdata[1] e18 linerxdata[2] d17 linerxdata[3] b17 linerxdata[4] d16 linerxdata[5] h16 linerxdata[6] e15 linerxdata[7] e14 linerxdata[8] d13 linerxdata[9] f14 linerxdata[10] a13 linerxdata[11] e13 linerxdata[12] f13 linerxdata[13] h13 linerxdata[14] a11 linerxdata[15] a9 linerxdata[16] a8 linerxdata[17] b8 linerxdata[18] e11 linerxdata[19] a7 linerxdata[20] d8 linerxdata[21] f11 linerxdata[22] c7 linerxdata[23] a6 linerxdata[24] f10 linerxdata[25] b6 linerxdata[26] c6 linerxdata[27] f8 linerxdata[28] a5 linerxdata[29] a4 linerxdata[30] e6 linerxdata[31] h6 linerxdata[32] g5 linerxdata[33] h8 linerxdata[34] g6 linerxdata[35] f5 linerxdata[36] h10 linerxdata[37] f12 linerxdata[38] c11 linerxdata[39] c12 linerxdata[40] h15 linerxdata[41] d15 linerxdata[42] a17 table 2-1. package pin assignments (continued) signal name pin linerxdata[43] h17 linerxdata[44] c18 linerxdata[45] a22 linerxdata[46] e21 linerxdata[47] d22 linerxdata[48] a26 linerxdata[49] h23 linerxdata[50] d25 linerxdata[51] a30 linerxdata[52] f25 linerxdata[53] a33 linerxdata[54] g27 linerxdata[55] e29 linerxdata[56] f28 linerxdata[57] g28 linerxdata[58] l29 linerxdata[59] l31 linerxdata[60] m29 linerxdata[61] n27 linerxdata[62] l32 linerxdata[63] k34 linerxdata[64] p30 linerxdata[65] m32 linerxdata[66] l34 linerxdata[67] m33 linerxdata[68] r27 linerxdata[69] p34 linerxdata[70] t32 linerxdata[71] u30 linerxdata[72] u34 linerxdata[73] v32 linerxdata[74] v31 linerxdata[75] w30 linerxdata[76] ab34 linerxdata[77] ac34 linerxdata[78] ad8 linerxdata[79] ae6 linerxdata[80] ac6 linerxdata[81] aa8 linerxdata[82] ag1 linerxdata[83] ab3 linerxdata[84] v9 linerxdata[85] w2 linerxdata[86] t1 linetxclk[1] k31 linetxclk[2] j34 linetxclk[3] h34 table 2-1. package pin assignments (continued) signal name pin
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 10 10 agere systems inc. linetxclk[4] j30 linetxclk[5] h32 linetxclk[6] h31 linetxclk[7] j29 linetxclk[8] g31 linetxclk[9] g30 linetxclk[10] h27 linetxclk[11] c31 linetxclk[12] j26 linetxclk[13] f27 linetxclk[14] f26 linetxclk[15] d28 linetxclk[16] c29 linetxclk[17] a31 linetxclk[18] e25 linetxclk[19] c28 linetxclk[20] b29 linetxclk[21] c27 linetxclk[22] d24 linetxclk[23] a28 linetxclk[24] a27 linetxclk[25] c24 linetxclk[26] a25 linetxclk[27] c23 linetxclk[28] a24 linetxclk[29] h21 linetxclk[30] a23 linetxclk[31] aa31 linetxclk[32] aa27 linetxclk[33] ad33 linetxclk[34] ab31 linetxclk[35] ab29 linetxclk[36] ad32 linetxclk[37] ac31 linetxclk[38] ab27 linetxclk[39] ag34 linetxclk[40] ad31 linetxclk[41] ad29 linetxclk[42] ad30 linetxclk[43] ag32 linetxclk[44] ae29 linetxclk[45] ae27 linetxclk[46] aj28 linetxclk[47] ak29 linetxclk[48] ah28 linetxclk[49] ah27 linetxclk[50] am31 table 2-1. package pin assignments (continued) signal name pin linetxclk[51] al28 linetxclk[52] al26 linetxclk[53] am27 linetxclk[54] ag22 linetxclk[55] al30 linetxclk[56] ag20 linetxclk[57] ag24 linetxclk[58] ag25 linetxclk[59] ak19 linetxclk[60] al19 linetxclk[61] af17 linetxclk[62] aj25 linetxclk[63] ah7 linetxclk[64] an18 linetxclk[65] aj12 linetxclk[66] ak12 linetxclk[67] an16 linetxclk[68] ak14 linetxclk[69] al4 linetxclk[70] ah6 linetxclk[71] al3 linetxclk[72] af9 linetxclk[73] aj4 linetxclk[74] ah4 linetxclk[75] ag5 linetxclk[76] af5 linetxclk[77] u3 linetxclk[78] n3 linetxclk[79] p5 linetxclk[80] p6 linetxclk[81] h1 linetxclk[82] g1 linetxclk[83] k8 linetxclk[84] f2 linetxclk[85] d1 linetxclk[86] h7 linetxdata[1] l27 linetxdata[2] k30 linetxdata[3] k29 linetxdata[4] j31 linetxdata[5] h33 linetxdata[6] k27 linetxdata[7] h30 linetxdata[8] h29 linetxdata[9] j27 linetxdata[10] g29 linetxdata[11] h28 table 2-1. package pin assignments (continued) signal name pin
hardware design guide, revision 6 tmxa84622 ultramapper full transport march 7, 2005 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 11 linetxdata[12] b32 linetxdata[13] e28 linetxdata[14] b31 linetxdata[15] e27 linetxdata[16] h25 linetxdata[17] e26 linetxdata[18] d27 linetxdata[19] d26 linetxdata[20] f24 linetxdata[21] e24 linetxdata[22] f23 linetxdata[23] b27 linetxdata[24] e23 linetxdata[25] d23 linetxdata[26] h22 linetxdata[27] e22 linetxdata[28] f21 linetxdata[29] b23 linetxdata[30] c22 linetxdata[31] aa29 linetxdata[32] ab32 linetxdata[33] ad34 linetxdata[34] aa30 linetxdata[35] ac32 linetxdata[36] ae34 linetxdata[37] ab30 linetxdata[38] af34 linetxdata[39] ac30 linetxdata[40] ac29 linetxdata[41] ag33 linetxdata[42] ae31 linetxdata[43] ac27 linetxdata[44] ae30 linetxdata[45] aj33 linetxdata[46] al31 linetxdata[47] am33 linetxdata[48] ak30 linetxdata[49] aj29 linetxdata[50] am32 linetxdata[51] an33 linetxdata[52] ak25 linetxdata[53] ak24 linetxdata[54] ak23 linetxdata[55] ap28 linetxdata[56] ap26 linetxdata[57] ap25 linetxdata[58] an24 table 2-1. package pin assignments (continued) signal name pin linetxdata[59] am22 linetxdata[60] ag18 linetxdata[61] am19 linetxdata[62] al18 linetxdata[63] an19 linetxdata[64] ak11 linetxdata[65] ak16 linetxdata[66] ap17 linetxdata[67] al15 linetxdata[68] ag8 linetxdata[69] ak5 linetxdata[70] aj5 linetxdata[71] ak4 linetxdata[72] ah5 linetxdata[73] ag6 linetxdata[74] al2 linetxdata[75] af6 linetxdata[76] aj3 linetxdata[77] n1 linetxdata[78] t8 linetxdata[79] l1 linetxdata[80] m3 linetxdata[81] m8 linetxdata[82] l4 linetxdata[83] h3 linetxdata[84] n8 linetxdata[85] e1 linetxdata[86] h5 lopohclkin b22 lopohclkout a21 lopohdatain d20 lopohdataout h19 lopohvalidin e20 lopohvalidout a20 losext ag27 lp_intn w1 mode0_pll aj31 mode1_pll ag30 mode2_pll ak31 mpclk g4 mpmode d2 nc n32 nc n33 nc p27 nc p31 nc r30 nc r31 table 2-1. package pin assignments (continued) signal name pin
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 12 12 agere systems inc. nc r34 nc t30 nc t31 nc t34 nc u27 nc u31 nc u32 nc v27 nc v33 nc v34 nc w27 nc w32 nc w33 nc y27 nc y31 nc y34 nc ab33 nc ad27 nc af29 nc af30 nc af31 nc ag28 nc ag29 nc ag31 nc ah29 nc ah32 nc ah33 nc ah34 nc aj30 nc aj32 nc aj34 nc ak26 nc ak27 nc al29 nc an32 nsmirxclk[1] aj22 nsmirxclk[2] ak28 nsmirxclk[3] ag21 nsmirxdata[1] am24 nsmirxdata[2] ap27 nsmirxdata[3] an27 nsmirxsync[1] al22 nsmirxsync[2] al23 nsmirxsync[3] ap29 nsmitxclk[1] ag23 nsmitxclk[2] ap31 nsmitxclk[3] an31 table 2-1. package pin assignments (continued) signal name pin nsmitxdata[1] an28 nsmitxdata[2] al25 nsmitxdata[3] ap33 nsmitxsync[1] ap30 nsmitxsync[2] ap32 nsmitxsync[3] al27 par[0] r1 par[1] u4 pmrst aj24 ref10 ak6 ref14 aj6 reshi al5 reslo al6 rhscn an1 rhscp am1 rhsdn am3 rhsdp am2 rhsfsyncn ap22 rlsclk aj14 rlsdatan[1] an10 rlsdatan[2] am10 rlsdatan[3] ap12 rlsdatap[1] ap10 rlsdatap[2] am9 rlsdatap[3] ap11 rpoacclk am17 rpoacdata ag17 rpoacsync ap19 rpscn am8 rpscp am7 rpsdn ap6 rpsdp an6 rstn ak18 rtoacclk am12 rtoacdata al12 rtoacsync an17 rwn j6 rxdataen[1] ak21 rxdataen[2] ak22 rxdataen[3] al24 scan_en aj23 scanmode ak20 sck1 ap24 sck2 am23 tck an22 tdi ap23 tdo aj21 table 2-1. package pin assignments (continued) signal name pin
hardware design guide, revision 6 tmxa84622 ultramapper full transport march 7, 2005 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 13 thscn ap4 thscon ap2 thscop an2 thscp an4 thsdn am6 thsdp am5 thssync al13 tlsclk ak13 tlsdatan[1] am11 tlsdatan[2] an13 tlsdatan[3] ag12 tlsdatap[1] an11 tlsdatap[2] an12 tlsdatap[3] ag11 tms an23 tpoacclk al17 tpoacdata ak17 tpoacsync ap20 tpscn ap8 tpscp an8 tpsdn an9 tpsdp ap9 trst ag26 tstmode aj13 tstphase ag15 tstsftld ag7 ttoacclk ah8 ttoacdata al16 ttoacsync ap18 txdataen[1] an29 txdataen[2] am28 txdataen[3] am29 v dd15 j10 v dd15 j13 v dd15 j17 v dd15 j18 v dd15 j22 v dd15 j25 v dd15 k9 v dd15 k17 v dd15 k18 v dd15 k26 v dd15 n9 v dd15 n13 v dd15 n14 v dd15 n15 v dd15 n16 table 2-1. package pin assignments (continued) signal name pin v dd15 n17 v dd15 n18 v dd15 n19 v dd15 n20 v dd15 n21 v dd15 n22 v dd15 n26 v dd15 p13 v dd15 p22 v dd15 r13 v dd15 r22 v dd15 t13 v dd15 t22 v dd15 u10 v dd15 u13 v dd15 u22 v dd15 u25 v dd15 u26 v dd15 v10 v dd15 v13 v dd15 v22 v dd15 v25 v dd15 v26 v dd15 w13 v dd15 w22 v dd15 y13 v dd15 y22 v dd15 aa9 v dd15 aa13 v dd15 aa22 v dd15 aa26 v dd15 ab9 v dd15 ab13 v dd15 ab14 v dd15 ab15 v dd15 ab16 v dd15 ab17 v dd15 ab18 v dd15 ab19 v dd15 ab20 v dd15 ab21 v dd15 ab22 v dd15 ab26 v dd15 ae9 v dd15 ae17 v dd15 ae18 v dd15 ae26 table 2-1. package pin assignments (continued) signal name pin
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 14 14 agere systems inc. v dd15 af10 v dd15 af13 v dd15 af14 v dd15 af18 v dd15 af21 v dd15 af22 v dd15 af25 v dd15 ah26 v dd15 aj26 v dd15 aj27 v dd15 j14 v dd15 j21 v dd15 p9 v dd15 p26 v dd15a_cdr1 ap14 v dd15a_cdr2 al11 v dd15a_ds3pll c19 v dd15a_e3pll b19 v dd15a_x4pll am16 v dd33 a2 v dd33 a3 v dd33 b1 v dd33 b3 v dd33 b5 v dd33 b9 v dd33 b10 v dd33 b14 v dd33 b15 v dd33 b20 v dd33 b21 v dd33 b25 v dd33 b26 v dd33 b30 v dd33 b33 v dd33 b34 v dd33 c2 v dd33 c4 v dd33 c32 v dd33 c33 v dd33 c34 v dd33 d3 v dd33 d5 v dd33 d32 v dd33 d33 v dd33 d34 v dd33 e2 v dd33 e4 table 2-1. package pin assignments (continued) signal name pin v dd33 e33 v dd33 e34 v dd33 j2 v dd33 j11 v dd33 j12 v dd33 j15 v dd33 j16 v dd33 j19 v dd33 j20 v dd33 j23 v dd33 j24 v dd33 j33 v dd33 k2 v dd33 k33 v dd33 l9 v dd33 l26 v dd33 m9 v dd33 m26 v dd33 p2 v dd33 p33 v dd33 r2 v dd33 r9 v dd33 r26 v dd33 r33 v dd33 t9 v dd33 t26 v dd33 w9 v dd33 w26 v dd33 y2 v dd33 y9 v dd33 y26 v dd33 y33 v dd33 aa2 v dd33 aa33 v dd33 ac9 v dd33 ac26 v dd33 ad9 v dd33 ad26 v dd33 ae2 v dd33 ae33 v dd33 af2 v dd33 af11 v dd33 af12 v dd33 af15 v dd33 af16 v dd33 af19 v dd33 af20 table 2-1. package pin assignments (continued) signal name pin
hardware design guide, revision 6 tmxa84622 ultramapper full transport march 7, 2005 622/155 mbits/s sonet/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 15 v dd33 af23 v dd33 af24 v dd33 af33 v dd33 ak2 v dd33 ak33 v dd33 ak34 v dd33 al33 v dd33 al34 v dd33 am34 v dd33 an14 v dd33 an15 v dd33 an20 v dd33 an21 v dd33 an25 v dd33 an26 v dd33 an30 v dd33 an34 v dd33a_sfpll ah30 v ss b2 v ss c3 v ss c5 v ss c9 v ss c10 v ss c14 v ss c15 v ss c20 v ss c21 v ss c25 v ss c26 v ss c30 v ss d4 v ss d31 v ss e3 v ss e31 v ss e32 v ss f30 v ss f31 v ss f32 v ss f33 v ss f34 v ss g32 v ss g33 v ss g34 v ss j3 v ss j32 v ss k3 v ss k32 table 2-1. package pin assignments (continued) signal name pin v ss p3 v ss p14 v ss p15 v ss p16 v ss p17 v ss p18 v ss p19 v ss p20 v ss p21 v ss p32 v ss r3 v ss r14 v ss r15 v ss r16 v ss r17 v ss r18 v ss r19 v ss r20 v ss r21 v ss r32 v ss t14 v ss t15 v ss t16 v ss t17 v ss t18 v ss t19 v ss t20 v ss t21 v ss u14 v ss u15 v ss u16 v ss u17 v ss u18 v ss u19 v ss u20 v ss u21 v ss v14 v ss v15 v ss v16 v ss v17 v ss v18 v ss v19 v ss v20 v ss v21 v ss w14 v ss w15 v ss w16 table 2-1. package pin assignments (continued) signal name pin
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 march 7, 2005 16 16 agere systems inc. v ss w17 v ss w18 v ss w19 v ss w20 v ss w21 v ss y3 v ss y14 v ss y15 v ss y16 v ss y17 v ss y18 v ss y19 v ss y20 v ss y21 v ss y32 v ss aa3 v ss aa14 v ss aa15 v ss aa16 v ss aa17 v ss aa18 v ss aa19 v ss aa20 v ss aa21 v ss aa32 v ss ae3 v ss ae32 v ss af3 v ss af32 v ss ag16 v ss ag19 v ss aj7 v ss aj8 v ss aj9 table 2-1. package pin assignments (continued) signal name pin v ss aj10 v ss aj11 v ss ak3 v ss ak7 v ss ak8 v ss ak9 v ss ak10 v ss ak32 v ss al7 v ss al8 v ss al9 v ss al10 v ss al32 v ss am4 v ss am14 v ss am15 v ss am20 v ss am21 v ss am25 v ss am26 v ss am30 v ss an3 v ss an5 v ss an7 v ss ap3 v ss ap5 v ss ap7 v ssa_cdr1 ap13 v ssa_cdr2 ag13 v ssa_ds3pll d18 v ssa_e3pll a19 v ssa_sfpll ah31 v ssa_x4pll ak15 table 2-1. package pin assignments (continued) signal name pin
agere systems inc. 17 hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 2.3 pin assignment matrix table 2-2. pin matrix 12 3 456789101112 a ? vdd33 vdd33 linerxdata[29] linerxdata[28] linerxdata[23] linerxdata[19] linerxdata[16] linerxdata[15] linerxclk [37] linerxdata [14] lin erxclk [38] b vdd33 vss vdd33 linerxclk[29] vdd33 linerxdata[25] linerxclk[20] linerxdata[17] vdd33 vdd33 linerxclk[13] linerxclk[11] c linerxclk[33] vdd33 vss vdd33 vss linerxdata[26] linerxdata[22] linerxclk[18] vss vss linerxdata[38] linerxdata[39] d linetxclk[85] mpmode vdd33 vss vdd33 linerxclk[27] linerxclk[23] liner xdata[20] linerxclk[17] linerxclk[15] linerxclk[12] linerxclk[10] e linetxdata[85] vdd33 vss vdd33 linerxclk[35] linerxdata[30] linerxclk[ 26] linerxclk[24] linerxclk[21] linerxclk[22] linerxdata[18] linerxc lk[14] f addr[6] linetxclk[84] adsn linerxclk[32] linerxdata[35] linerxclk[36] li nerxclk[30] linerxdata[27] linerxclk[25] linerxdata[24] linerxdat a[21] linerxdata[37] g linetxclk[82] addr[7] addr[2] mpclk linerxdat a[32] linerxdata[34] csn linerxclk[28] ? ? ? ? h linetxclk[81] addr[10] linetxdata[83] addr[1] linetxdata[86] linerxdata [31] linetxclk[86] linerxdata[33] linerxclk[34] linerxdata[36] lin erxclk[19] linerxclk[16] j addr[16] vdd33 vss addr[4] dsn rwn ? addr[3] linerxclk[31] vdd15 vdd33 vdd33 k data[0] vdd33 vss addr[12] addr[5] addr[0] ? linetxclk[83] vdd15 ? ? ? l linetxdata[79] data[1] addr[17] linetxdata[82] addr[9] addr[8] ? addr[13] vdd33 ? ? ? m data[7] data[5] linetxdata[80] addr[18] addr[14] addr[11] ? linetxdata[81] vdd33 ? ? ? n linetxdata[77] data[11] linetxclk[78] data[3] addr[20] addr[15] ? linetxdata[84] vdd15 ? ? ? p data[15] vdd33 vss data[10] linetxclk[79] linetxclk[80] ? addr[19] vdd15 ? ? ? r par[0] vdd33 vss data[12] data[8] ? ? data[4] vdd33 ? ? ? t linerxdata[86] linerxclk[86] dtn data[13] data[6] ? ? linetxdata[78] vdd33 ? ? ? u linerxclk[85] data[2] linetxclk[77] par [1] data[9] ? ? hp_intn data[14] vdd15 ? ? v ds3negdatain[1] ds3posdataout[1] ds3datainclk[3] ds3datainclk[2] ds3posdatain[4] ? ? ds2aisclk linerxdata[84] vdd15 ? ? w lp_intn linerxdata[85] ds3posdatain[1] linerxclk[84] ds3posdatain[6] ? ? ds3posdatain[5] vdd33 ? ? ? y aps_intn vdd33 vss ds3negdatain[3] ds3negdatain[5] ? ? linerxclk[82] vdd33 ? ? ? aa e2aisclk vdd33 vss linerxclk[83] ds3negdatain[ 6] ds3posdataout[2] ? linerxdata[81] vdd15 ? ? ? ab ds3datainclk[1] ds3posdatain[2] linerxdata[83] ds3datainclk[6] ds3dataoutclk[1] ds3rxclkout[3] ? ds3dataoutclk[2] vdd15 ? ? ? ac ds3negdatain[2] ds3negdatain[4] ds3negdataout[1] ds3negdataout[2] ds3dataoutclk[3] linerxdata[80] ? ds3rxclkout[4] vdd33 ? ? ? ad ds3posdatain[3] ds3rxclkout[1] ds3rxclkout[2] linerxclk[81] ds3dataoutclk[4] ds3rxclkout[5] ? linerxdata[78] vdd33 ? ? ? ae ds3datainclk[4] vdd33 vss linerxclk[80] ds3dataoutclk[5] linerxdata[79] ? ds3rxclkout[6] vdd15 ? ? ? af ds3datainclk[5] vdd33 vss ds3posdataout[6] linetxclk[76] linetxdata[75] ? ctaprh linetxclk[72] vdd15 vdd33 vdd33 ag linerxdata[82] ds3posdataout[5] ds3negdtataout[5] ds3dataoutclk[6] l inetxclk[75] linetxdata[73] tstsftld linetxdata[68] ctapth ctaprp tls datap[3] tlsdatan[3] ah ds3posdataout[3] linerxclk[79] linerxc lk[78] linetxclk[74] linetxdata[72] linetxclk[70] linetxclk[63] ttoacclk ? ? ? ? aj ds3negdataout[3] ds3negdataout[6] linetxdata[76] linetxclk[73] linetxdata[70] ref14 vss vss vss vss vss linetxclk[65] ak ds3posdataout[4] vdd33 vss linetxdata[71] linetxdata [69] ref10 vss vss vss vss linetxdata[64] linetxclk[66] al ds3negdataout[4] linetx data[74] linetxclk[71] linetxclk[69] reshi reslo vss vss vss vss vdd15a_cdr2 rtoacdata am rhscp rhsdp rhsdn vss thsdp thsdn rpscp rpscn rlsdatap[2] rlsdatan[2] tlsdatan[1] rtoacclk an rhscn thscop vss thscp vss rpsdp vss tpscp tpsdn rlsdatan[1] tlsdatap[1] tlsdatap[2] ap ?thsconvss thscn vss rpsdn vss tpscn tpsdp rlsdatap[1] rlsdatap[3] rlsdatan[3]
18 agere systems inc. tmxa84622 ultramapper full transport hardware d esign guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 table 2-2. pin matrix (continued) 13 14 15 16 17 18 19 20 21 22 23 a linerxdata [10] linerxclk [7] linerxclk [6] l inerxclk [41] linerxdata [42] linerxclk [1] v ssa_e3pll lopohvalidout lopohclkout linerxdata [45] linetxclk[30] b linerxclk[9] vdd33 vdd33 linerxclk[5] linerxdata[3] linerxc lk[43] vdd15a_e3pll vdd33 vdd33 lopohclkin linetxdata[29] c linerxclk[8] vss vss linerxclk[4] linerx clk[2] linerxdata[44] vdd15a_ds3pll vss vss linetxdata[30] linetxclk[27] d linerxdata[8] linerxclk[40] linerxdata[41] linerxdata[4] linerxdata[ 2] vssa_ds3pll linerxclk[44] lopohdatain linerxclk[46] linerxdata[47 ] linetxdata[25] e linerxdata[11] linerxdata[7] linerxdata[6] li nerxclk[3] linerxclk[42] linerxdata[1] ds3xclk lopohvalidin linerxdata[46] linetxdata[27] li netxdata[24] f linerxdata[12]linerxdata[9]??????linetxdata[28]linerxclk[48]linetxdata[22] g ??????????? h linerxdata[13] linerxclk[39] linerx data[40] linerxdata[5] linerxdata[43] e3xclk lopohdat aout linerxclk[45] linetxclk[29] linetxdata[26] l inerxdata[49] j vdd15 vdd15 vdd33 vdd33 vdd15 vdd15 vdd33 vdd33 vdd15 vdd15 vdd33 k ????vdd15vdd15????? l ??????????? m ??????????? n vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 ? p vdd15 vss vss vss vss vss vss vss vss vdd15 ? r vdd15 vss vss vss vss vss vss vss vss vdd15 ? t vdd15 vss vss vss vss vss vss vss vss vdd15 ? u vdd15 vss vss vss vss vss vss vss vss vdd15 ? v vdd15 vss vss vss vss vss vss vss vss vdd15 ? w vdd15 vss vss vss vss vss vss vss vss vdd15 ? y vdd15 vss vss vss vss vss vss vss vss vdd15 ? aa vdd15 vss vss vss vss vss vss vss vss vdd15 ? ab vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 vdd15 ? ac ??????????? ad ??????????? ae ????vdd15vdd15????? af vdd15 vdd15 vdd33 vdd33 linetxclk[61] vdd15 vdd33 vdd33 vdd15 vdd15 vdd33 ag vssa_cdr2 ctaptl tstphase vss rpoacdata linetxdata[60] vss l inetxclk[56] nsmirxclk[3] li netxclk[54] nsmitxclk[1] ah ??????????? aj tstmoderlsclk??????tdonsmirxclk[1]scan_en ak tlsclk linetxclk[68] vssa_x4pll linetxdata[65] tpoacdata rstn lin etxclk[59] scanmode rxdataen[1] rxdataen[2] linetxdata[54] al thssync ecsel linetxdata[67] ttoacdata tpoacclk linetxdata[62] linetxclk[60] ic3staten iddq nsmirxsync[1] nsmirxsync[2] am bypass vss vss vdd15a_x4pll rpoacclk e1xclk linetxdata[61] vss vss linetxdata[59] sck2 an tlsdatan[2] vdd33 vdd33 linetxclk[67] rtoacsync linetxclk[64] linetxdata[63] vdd33 vdd33 tck tms ap vssa_cdr1 vdd15a_cdr1 etoggle exdnup linetxdata[66] ttoacsync rpoacsync tpoacsync ds1xclk rhsfsyncn tdi
agere systems inc. 19 hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 table 2-2. pin matrix (continued) 24 25 26 27 28 29 30 31 32 33 34 a linetxclk[28] linetxclk[ 26] linerxdata[48] linetxclk[24] linetxclk[23] linerxclk[ 50] linerxdata[51] linetxclk[ 17] linerxclk[52] linerxda ta[53] ? b linerxclk[47] vdd33 vdd33 linetxdata[23] linerxclk[49] lin etxclk[20] vdd33 linetxdata[14] linetxdata[12] vdd33 vdd33 c linetxclk[25] vss vss linetxclk[21] linetxclk[19] linetxclk[16] vss linetxclk[11] vdd33 vdd33 vdd33 d linetxclk[22] linerxdata[50] li netxdata[19] linetxdata[18] linetxclk[15] li nerxclk[53] linerxclk[54] vss vdd33 vdd33 vdd33 e linetxdata[21] linetxclk[18] li netxdata[17] linetxdata[15] li netxdata[13] linerxdata[55] li nerxclk[56] vss vss vdd33 vdd33 f linetxdata[20] linerxdata[52] line txclk[14] linetxclk[13] linerxdata [56] linerxclk[57] vss vss vss vss vss g ? ? ? linerxdata[54] linerxdata [57] linetxdata[10] linetxclk[9] linetxclk[8] vss vss vss h linerxclk[51] linetxdata[16] linerxclk[55] line txclk[10] linetxdata[11] linetxdata[8] linetxdata[7] linetxclk[6] linetxclk[5] linetxdata [5] linetxclk[3] j vdd33 vdd15 linetxclk[12] linetxdata[9] ? linetxclk[7] linetxclk[4] linetxdata[4] vss vdd33 linetxclk[2] k ? ? vdd15 linetxdata[6] ? linetxdata[3] linetxdata[2] linetxclk[1] vss vdd33 linerxdata[63] l ? ? vdd33 linetxdata[1] ? linerxdata[58] linerxclk[58] line rxdata[59] linerxdata[62] li nerxclk[64] linerxdata[66] m ? ? vdd33 linerxclk[59] ? linerxdata[60] linerxclk[60] line rclk[62] linerxdata[65] line rxdata[67] linerxclk[67] n ? ? vdd15 linerxdata[61] ? linerxclk[61] line rxclk[63] linerxclk[65] nc nc linerxclk[68] p ? ? vdd15 nc ? linerxclk[66] linerxdata[64] nc vss vdd33 linerxdata[69] r ? ? vdd33 linerxdata[68] ? ? nc nc vss vdd33 nc t ? ? vdd33 linerxclk[69] ? ? nc nc linerxdata[70] linerxclk[70] nc u ? vdd15 vdd15 nc ? ? linerxdata[71] nc nc linerxclk[71] linerxdata[72] v ? vdd15 vdd15 nc ? ? linerxclk[72] linerxdata[74] linerxdata[73] nc nc w ? ? vdd33 nc ? ? linerxdata[75] linerxclk[74] nc nc linerxclk[73] y ? ? vdd33 nc ? ? linerxclk[76] nc vss vdd33 nc aa ? ? vdd15 linetxclk[32] ? linetxdata[31] linetx data[34] linetxclk[31] vss vdd33 linerxclk[75] ab ? ? vdd15 linetxclk[38] ? linetxclk[35] linetxdata[ 37] linetxclk[34] linetxdata[32] nc linerxdata[76] ac ? ? vdd33 linetxdata[43] ? linetxdata[40] linetxdata[39] li netxclk[37] linetxdata[35] li nerxclk[77] linerxdata[77] ad ? ? vdd33 nc ? linetxclk[41] linetxclk[42] linetxcl k[40] linetxclk[36] linet xclk[33] linetxdata[33] ae ? ? vdd15 linetxclk[45] ? linetxclk[44] linetxdata[44] linetxdata[42] vss vdd33 linetxdata[36] af vdd33 vdd15 cg_pllclkout clkin_pll ? nc nc nc vss vdd33 linetxdata[38] ag linetxclk[57] linetxclk[58] trst losext nc nc mode1_pl l nc linetxclk[43] linetxdata[41] linetxclk[39] ah ? ? vdd15 linetxclk[49] linetxclk[48] nc vdd33a_sfpll vssa_sfpll nc nc nc aj pmrst linetxclk[62] vdd15 vdd15 linetxclk[46] li netxdata[49] nc mode0_p ll nc linetxdata[45] nc ak linetxdata[53] linetxdata[52] nc nc nsmirxclk[2] li netxclk[47] linetxdata[48] mode2_pll vss vdd33 vdd33 al rxdataen[3] nsmitxdata[2] linetxclk[52] nsmitxsync[3] li netxclk[51] nc linetxclk[55] linetxdata[46] vss vdd33 vdd33 am nsmirxdata[1] vss vss linetxclk[53] txdataen[2] txdataen[3 ] vss linetxclk[50] linetxdata[50] linetxdata[47] vdd33 an linetxdata[58] vdd33 vdd33 nsmirxdata[3] nsmitxdata[1] txdataen[1] vdd33 nsmitxclk[3] nc linetxdata[51] vdd33 ap sck1 linetxdata[57] linetxdata[56] nsmirxdata[2] linetxdata[55] nsmirxsync[3] nsmitxsync[1] nsmitxclk[2] nsmitxsync[2] nsmitxdata[3] ?
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 20 20 agere systems inc. 2.4 pin types table 2-3 describes each type of input, output, and i/o pin used in the ultramapper full transport device. table 2-3. pin types type label description i lvcmos input, lvttl switching thresholds. i pd lvcmos input, lvttl switching thresholds with internal 50 k ? pull-down resistor. i pu lvcmos input, lvttl switching thresholds with internal 50 k ? pull-up resistor. o lvcmos output. o od open-drain output. l in lvds inputs. l out lvds outputs. i/o bidirectional pin. lvcmos input with lvttl switchin g thresholds and lvcmos output. i/o pd bidirectional pin. lvcmos input with lvttl switchin g thresholds with internal 50 k ? pull-down resistor and lvcmos output. ? power, ground, analog inputs for external resistors, capacitors, voltage references, etc. nc no connect.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 21 2.5 pin definitions this section describes the function of each of the de vice pins. all lvds input buffers have a built-in 100 ? terminating resistor with a center tap pin available for an external capacitor connection. all unused lvds inputs may be left unconnected. pin functionality is desc riptive information. the actual func tionality is dependent upon the device configuration via the registers. table 2-4. tmux block, high-speed interface i/o pin symbol type name/description am2 rhsdp l in receive high-speed data. 622/155 mbits/s input data. this is also an input to internal clock and data recovery (cdr). cdr may be bypassed in 155 mbits/s mode. in 622 mbits/s mode, the internal cdr must be used. am3 rhsdn am1 rhscp l in receive high-speed clock. 155 mhz input clock for 155 mbits/s da ta if cdr is bypassed. not used in 622 mbits/s mode. an1 rhscn af8 ctaprh ? center tap rh. lvds buffer terminator center tap for rhsdp/n and rhscp/n. an optional 0.1 f capacitor, connected between ctap pi n and ground, will improv e the common-mode re- jection of the lvds input buffers. ag27 losext i pu external loss-of-signal input . active level is programmable by register tmux_losext_level. defaults to active-low. th is pin can be part of the high-priority interrupt when active. usually co nnected to optical transceiver to indicate loss of signal. am5 thsdp l out transmit high-speed data. 622/155 mbits/s output data. the frame location in slave mode is determined by thssync and transmit high-speed control parameter register (tmux_tframeoffseta). in master mode, the frame timing is arbitrary. am6 thsdn an2 thscop l out transmit high-speed clock output. 622/155 mhz transmit output clock associated with thsdp/n. ap2 thscon al5 reshi ? resistor. a 100 ? , 1% resistor is required between the reshi and reslo pins as a refer- ence for the lvds input buffer termination. al6 reslo ak6 ref10 * i reference 1.0 v. external 1 v reference voltage pin (optional). aj6 ref14 * i reference 1.4 v. external 1.4 v reference voltage pin (optional). * optional: selected by mpu/top-level register umpr_lvds_ref_sel. external reference voltage can be sourced from a low-impedance resistor (less than 1 k ? ) divider circuit decoupled with a 0.1 f capacitor. please refer to table 4-4 lvds interface dc characteristics on page 40 for addi- tional information. table 2-5. tmux block, protection link i/o pin symbol type name/description an6 rpsdp l in receive protection high-speed data. 622/155 mbits/s protection input data. also input to in- ternal protection cdr. cdr may be bypassed in 155 mbits/s mode. in 622 mbits/s mode, the internal cdr must be used. ap6 rpsdn am7 rpscp l in receive protection high-speed clock. 155 mhz input clock for 155 mbits/s data if protection cdr is bypassed. not used in 622 mbits/s mode. am8 rpscn ag10 ctaprp ? center tap rp. lvds buffer terminator center tap for rpsdp/n and rpscp/n. an optional 0.1 f capacitor, connected between ctap pi n and ground, will improv e the common-mode re- jection of the lvds input buffers. ap9 tpsdp l out transmit protection high-speed data. 622/155 mbits/s protec tion output data. an9 tpsdn an8 tpscp l out transmit protection high-speed clock. 622/155 mhz transmit output clock associated with tpsdp/n. ap8 tpscn
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 22 22 agere systems inc. table 2-6. tmux block, clock and sync i/o pin symbol type name/description an4 thscp l in transmit high-speed clock. 622 mhz/155 mhz input clock for transmit 622/155 mbits/s data. also used as a reference clock for a ll cdrs. there are five cdr circuits. the high- speed data and protection high-speed data have cdrs that operate at 155 mhz or 622 mhz. the mate inputs have three cdrs that operate at 155 mhz. the clock on this pin is also internally routed to the ds1/e1 fram ers and is used as an internal master clock. note: a 622 mhz clock must be supplied when the device operates in 622 mbits/s mode. a 155 mhz clock must be supplied when the de vice operates in 155 mbits/s mode. for version 3.0 devices and later, the following applies: a 622 mhz clock must be supplied when the device operates in 622 mbits/s mode. a 155 mhz or 622 mhz clock can be supplied when the device operates in 155 mbits/s mode (choice provisionable via umpr_oc3thsc_mode). ap4 thscn ag9 ctapth ? center tap th. lvds buffer terminator center tap for thscp/n. an optional 0.1 f capaci- tor, connected between ctap pin and ground will improve t he common-mode rejection of the lvds input buffers. ap22 rhsfsyncn o receive high-speed frame sync. this output indicates the start of the frame in the high- speed data input. only present when a valid frame signal is detected on the rhsdp/n inputs. it is an active-low pulse with a pulse width almost equal to one e1 clock period, or approximately 500 ns. aj14 rlsclk o receive low-speed clock. 19.44 mhz receive output clock divided down from either rhscp/n or the recovered high-speed clock (when the cdr is used). may be used as a system timing reference. ak13 tlsclk o transmit low-speed clock. 19.44 mhz transmit output clock divided down from thscp/n. al13 thssync i/o pd transmit high-speed frame sync. 2 khz/8 khz composite frame sync signal that identi- fies the locations of the j 0 , j 1-1 , j 1-2 , j 1-3 . . . j 1-12 , and v 1-1 bytes. this signal is used to align transmit frames before multiplexing. note: j 0 , j 1-1 , j 1-2 , and j 1-3 . . . j 1-12 occur every 125 s. v 1-1 occurs every 500 s. if the register mpu_master_slave = 1, th ssync is an output; ot herwise, thssync is an input. the positive 8 khz and 2 khz pu lses are synchronized to tl sclk (in master mode only). the rising edge is referenced for frame lo cation. for master/slave configuration, the thssync of all ultramapper full transports (up to four) must be connected together. the master can be one of the ultramapper full transports, and it sources the frame sync pulse to other ultramapper full transports. all ultramapper full transports can also be configured as slaves and receive frame sync fr om the external system frame sync.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 23 table 2-7. sts cross-connect (stsxc) block, sts-3/stm-1 mate interconnect pin symbol type name/description ap11, am9, ap10 rlsdatap[3:1] l out receive low-speed data. these pins are usually used in 622 mbits/s applica- tions (however, they can be used in a 1 55 mbits/s application). these pins are used on the device interfacing to the high-speed sts-n/stm-n line. connect these pins to the high-speed data in puts (rhsdp/n) of the slave devices. this 155 mbits/s signal uses a sonet stru cture. the overhead supported are the a1/a2 and b2 bytes and line rdi. the data is scrambled. data from the rhsd is routed via the stsxc. ap12, am10, an10 rlsdatan[3:1] ag11, an12, an11 tlsdatap[3:1] l in transmit low-speed data. these pins are usually used in 622 mbits/s applica- tions (however, they can be used in a 155 mbits/s application). these pins are used on the device interfacing to the high-spe ed sts-n/stm-n line. these pins should be connected to the high-speed data out puts (thsdp/n) of the slave devices. this 155 mbits/s input receives data from the slave high-speed outputs. these inputs have built-in clock and data recovery (cdr). the frame location ex- pects a fixed relationship to the hi gh-speed transmit frame sync (thssync). ag12, an13, am11 tlsdatan[3:1] ag14 ctaptl ? center tap tl. lvds buffer terminator center tap for tlsdatap/n. an optional 0.1 f capacitor, connec ted between ctap pi n and ground, will improve the com- mon-mode rejection of the lvds input buffers. table 2-8. multirate cross-connect (mrxc) block, toac input and output channels pin symbol type name/description am12 rtoacclk o receive transport overhead access channel clock. the frequency of this clock is determined by the toac provisioning registers. al12 rtoacdata o receive transport overhead access channel data. 622/155 mbits/s transport overhead bytes are output on this pin. the content is deter mined by the toac provisioning registers. an17 rtoacsync o receive transport overhead access channel sync. active-high 8 khz frame sync. it is active during the clock pe riod of the first bit of each frame. ah8 ttoacclk o transmit transport overhead access channel clock. the frequency of this clock is determined by the toac provisioning registers. al16 ttoacdata i pd transmit transport overhead access channel data. input for the transport overhead bytes. ap18 ttoacsync o transmit transport overhead access channel sync. active-high 8 khz frame sync. it is active during the clock pe riod of the first bit of each frame.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 24 24 agere systems inc. table 2-9. multirate cross-connect (mrxc) block, poac input and output channels pin symbol type name/description am17 rpoacclk o receive path overhead access channel clock. output for the path overhead bytes. this is a 3-state output pin controlled by register provisioning. ag17 rpoacdata o receive path overhead access channel data. output for the path overhead bytes. this pin can be 3-stated. ap19 rpoacsync o receive path overhead access channel sync. output for poac channel. ac- tive-high during the first bit of each fram e when the poac is connected to either the tmux or sts1lt. active-high during the lsb of the last byte of the frame when connected to the spempr. this pin can be indivi dually 3-stated. al17 tpoacclk o transmit path overhead access channel clock. serial access channel clock output for the path overhead bytes. th is pin can be individually 3-stated. ak17 tpoacdata i pd transmit path overhead access channel data. serial access channel data in- put for the path overhead bytes. ap20 tpoacsync o transmit path overhead access channel sync. output for poac channel. ac- tive-high during the first bit of each fram e when the poac is connected to either the tmux, the sts1lt, or the spempr. this pin can be indivi dually 3-stated. table 2-10. ds3/e3/sts-1 out pin symbol type name/description af4, ag2, ak1, ah1, aa6, v2 ds3posdataout[6:1] o ds3/e3/sts-1 positive data output. either contains the positive rail of the b3zs/hdb3 encoded output data, or single-rail nrz data. aj2, ag3, al1, aj1, ac4, ac3 ds3negdataout[6:1] o ds3/e3/sts-1 negative data output. negative-rail b3zs/hdb3 en- coded output data. not used in single-rail mode (held low in this case). ag4, ae5, ad5, ac5, ab8, ab5 ds3dataoutclk[6:1] i pd ds3/e3/sts-1 data output clock. 44.736 mhz, 34.368 mhz, or 51.84 mhz clock input and is typicall y connected to a crystal oscillator or clocking chip. this clock is required for m13, e13, or sts1lt applications and is typically connected to an oscillato r. this clock is not required for ds3/e3 to sonet/sdh mapping applications. in this case, ds3xclk/e3xclk is needed for ds3/e3 dja. for sts-1 to sonet mapping applications, the tmux can be used to supply the sts-1 rate dataout clock and this clock is therefore not needed. for sts-1 ? pdh applications, a 51.84 mhz clock must be sup- plied at this pin. ae8, ad6, ac8, ab6, ad3, ad2 ds3rxclkout[6:1] o ds3/e3/sts-1 receive clock output. 44.736 mhz ds3/34.368 mhz e3/51.84 mhz sts-1 clock out to external circuit. table 2-11. ds3/e3/sts-1 in pin symbol type name/description w5, w8, v5, ad1, ab2, w3 ds3posdatain[6:1] i pd ds3/e3/sts-1 positive data input. either contains the positive rail of the b3zs/hdb3 encoded input data, or single-rail nrz data. aa5, y5, ac2, y4, ac1, v1 ds3negdatain[6:1] i pd ds3/e3/sts-1 negative data input. either contains the negative rail of the b3zs/hdb3 encoded input data, or in single-rail mode, this input may be used to count bipolar violations. ab4, af1, ae1, v3, v4, ab1 ds3datainclk[6:1] i pd ds3/e3/sts-1 data input clock. 44.736 mhz, 34.368 mhz, or 51.84 mhz clock for the ds3/e3/sts-1 positive and negative data inputs.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 25 table 2-12. nsmi/sts-1 in pin symbol type name/description an27, ap27, am24 nsmirxdata[3:1] i pd network serial multiplex interface (nsmi) receive * data. this is used in the following applications: ? sts-1 rate clear-channel receive data to spempr. ? ds3/e3 rate clear-channel receive data to m13/e13. additionally, it could be used as a sonet compliant sts-1 input signal to sts1lt from external liu. for v3 .0 devices, these pins may also be used for ds3 clear channel (positive-ra il or single-rail) input data (to the spempr block). * the transmit path is toward the high-speed fiber output, a nd the receive path is from the high-speed input. low-speed inputs , e.g., nsmirxdata, on the transmit path, are labeled receive . low-speed outputs, e.g., nsmitxdata, on the receive path, are labeled transmit . ag21, ak28, aj22 nsmirxclk[3:1] i/o pd nsmi receive clock. used in the following applications: ? output (51.84 mhz) for the sts-1 rate clear-channel application. ? output (44.736 mhz/34.368 mhz) for the ds3/e3 application. additionally, it could be used as an input clock for sonet compliant sts-1 to sts1lt from external liu. for v3.0 devices, these pins may also be used for ds3 clear channel ds3 rate input clock for positive (and negative) data inputs. ap29, al23, al22 nsmirxsync[3:1] i/o pd nsmi receive frame sync. used in the following applications: ? output receive control frame sync signal for m13/e13. ? output receive control fr ame sync signal for spempr. additionally, it could be used to carry sts-1 input transmit clock for sts1lts. for v3.0 devices, these pins may also be used for ds3 clear channel negative-ra il input data (to the spempr block). al24, ak22, ak21 rxdataen[3:1] o nsmi receive data enable. in the spempr nsmi mode, the signal on this output will be high during the poh of the spe. in m13 nsmi mode, the signal output on this pin goes low during the m1 byte of the first m1 frame of the ds3 frame. in e13 nsmi mode, the signal output on this pin goes low during the over- head bytes and control bits of the e3 frame.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 26 26 agere systems inc. table 2-13. nsmi/sts-1 out pin symbol type name/description ap33, al25, an28 nsmitxdata[3:1] o nsmi transmit data.* nsmi outputs or sts-1 tx data outputs from sts1lts. nsmi output data from ei ther the spempr or m13/e13 block. for v3.0 devices, these pins may also be used for ds3 clear channel (positive-rail or single -rail) output data (from the ds3dja block). an31, ap31, ag23 nsmitxclk[3:1] o nsmi transmit clock output or sts-1 tx clock outputs from sts1lts. output clock at 51.84 mhz for the sts-1 rate clear-channel application, or the ds3/e3 applicat ion (44.736/34.368 mhz). for v3.0 devices, these pins may also be used for ds3 clear channel ds3 rate output clock (from the ds3dja block). al27, ap32, ap30 nsmitxsync[3:1] o transmit system frame sync output. output transmit control frame sync signal from m13/e13 or spempr . for v3.0 devices, these pins may also be used for ds3 clear channel negative-rail output data (from the ds3dja block). am29, am28, an29 txdataen[3:1] o transmit data enable for ns mi mode. in spempr nsmi mode, the sig- nal on this output will be hi gh during the poh of the spe. in m13 nsmi mode, the signal output on this pin goes low during the m1 byte of the first m1 frame of the ds3 frame. in e13 nsmi mode, the signal output on this pin goes low during the over- head bytes and control bits of the e3 frame. * the transmit path is toward the high-speed fiber output, and t he receive path is from the high-speed input. low-speed inputs, e.g., nsmirxdata, on the transmit path, are labeled receive . low-speed outputs, e.g., nsmitxdata, on the receive path, are labeled transmit .
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 27 the transmit path is toward the high-speed fiber output, an d the receive path is from the high-speed input. low-speed inputs, e.g., linerxdata, on the transmit path, are labeled receive . low-speed outputs, e.g., linetxdata, on the receive path, are labeled transmit . table 2-14. shared low-speed line in pin symbol type name/description t1, w2, v9, ab3, ag1, aa8, ac6, ae6, ad8, ac34, ab34, w30, v31, v32, u34, u30, t32, p34, r27, m33, l34, m32, p30, k34, l32, n27, m29, l31, l29, g28, f28, e29, g27, a33, f25, a30, d25, h23, a26, d22, e21, a22, c18, h17, a17, d15, h15, c12, c11, f12, h10, f5, g6, h8, g5, h6 , e6, a4, a5, f8, c6, b6, f10, a6, c7, f11, d8 , a7, e11, b8, a8, a9, a11, h13, f13, e13, a13, f14, d13, e14, e15, h16, d16, b17, d17, e18 linerxdata[86:1] i pd line receive data [86:1]. inputs to the internal multirate crossconnect. these signals are used for received single-rail ds1/e1 line data input, sourced from an exter- nal liu. in this mode, these signals will be rout- ed via the crossconnect to the vt mapper, the m13 multiplexer, e13 mult iplexer, or the receive line inputs of the ds1/e1 framers. these signals may also be used as input data for ds2/e2 applications (see the ultramapper family system design guide ). t2, u1, w4, aa4, y8, ad4, ae4, ah2, ah3, ac33, y30, aa34, w31, w34, v30, u33, t33, t27, n34, m34, p29, n31, l33, n30, m31, n29, m30, m27, l30, f29, e30, h26, d30, d29, a32, h24, a29, b28, f22, b24, d21, h20, d19, b18, e17, a16, d14, h14, a12, a10, f6, e5, h9, c1, f4, j9, f7, b4, g8, d6, e7, f9, e8, d7, e10, e9, b7, h11, c8, d9, h12, d10, e12, b11, d11, b12, d12, b13, c13, a14, a15, b16, c16, e16, c17, a18 linerxclk[86:1] i/0 pd line receive clock [86:1]. configurable inputs to the internal multirate crossconnect. these inputs are used for asynchronous clocks associated with the line receive data inputs from external line interface units, or payload termination functions. in certain cases, these pins can be used as outputs. these pins may be used for ds2/e2 clocks in ds2/e2 app lications. more informa- tion will be published in the ultramapper fam- ily system design guide.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 28 28 agere systems inc. the transmit path is toward the high-speed fiber output, an d the receive path is from the high-speed input. low-speed inputs, e.g., linerxdata, on the transmit path, are labeled receive . low-speed outputs, e.g., linetxdata, on the receive path, are labeled transmit . table 2-15. shared low-speed line out pin symbol type name/description h5, e1, n8, h3, l4, m8, m3, l1, t8, n1, aj3, af6, al2, ag6, ah5, ak4, aj5, ak5, ag8, al15, ap17, ak16, ak11, an19, al18, am19, ag18, am22, an24, ap25, ap26, ap28, ak23, ak24, ak25, an33, am32, aj29, ak30, am33, al31, aj33, ae30, ac27, ae31, ag33, ac29, ac30, af34, ab30, ae34, ac32, aa30, ad34, ab32, aa29, c22, b23, f21, e22, h22, d23, e23, b27, f23, e24, f24, d26, d27, e26, h25, e27, b31, e28, b32, h28, g29, j27, h29, h30, k27, h33, j31, k29, k30, l27 linetxdata[86:1] o line transmit data [86:1]. outputs from the internal multirate crossconnect. these signals are used for transmit of single-rail ds1/e1 line data output, sourced to an external liu. in this mode, th ese signals will be routed via the cross connect from the vt mapper, the m13 multiplexer, the e13 multiple xer, or the transmit line outputs of the ds1/e1 framers. each of these outputs comes from the internal mrxc and can be individually set to high imped- ance. these pins may also be used for output data in ds2/e2 applications (see the ultramapper family system design guide ). h7, d1, f2, k8, g1, h1, p6, p5, n3, u3, af5, ag5, ah4, aj4, af9, al3, ah6, al4, ak14, an16, ak12, aj12, an18, ah7, aj25, af17, al19, ak19, ag25, ag24, ag20, al30, ag22, am27, al26, al28, am31, ah27, ah28, ak29, aj28, ae27, ae29, ag32, ad30, ad29, ad31, ag34, ab27, ac31, ad32, ab29, ab31, ad33, aa27, aa31, a23, h21, a24, c23, a25, c24, a27, a28, d24, c27, b29, c28, e25, a31, c29, d28, f26, f27, j26, c31, h27, g30, g31, j29, h31, h32, j30, h34, j34, k31 linetxclk[86:1] i/o pd line transmit clock [86:1]. configurable outputs from the internal multirate cross connect. these outputs are used for asynchronous clocks, associated with the line transmit data outputs to external line interface units or payload termination functions. each of these outputs comes from the internal mrxc and can be individually set to high impedance. in certain cases, these pins can be used as an input (input ds2/e2 clocks). more information will be published in the ultramapper family system design guide .
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 29 table 2-16. reference clocks pin symbol type name/description v8 ds2aisclk i pd ds2 ais clock. see application note: configuring ultramapper family of devices for ported ds2 applications . if used, this input can be prov ided by a free-running crystal or clocking chip. aa1 e2aisclk i pd e2 ais clock. see application note: configuring ultramapper family of devices for ported ds2 applications . if used, this input can be prov ided by a free-running crystal or clocking chip. am18 e1xclk i pd e1 x clock. this clock signal is used for three pu rposes: to generate e1 ais (all 1s), as a reference to the e1 dja, and as a clock source for the test pattern generator and test pat- tern monitor. this input may be provided by a 2.048 mhz, a 32.768 mhz, or a 65.536 mhz 50 ppm free-r unning crystal oscillator or clocking chip. note: for the e1 dja, an input of 32.768 mhz or 65.536 mhz must be used. ap21 ds1xclk i pd ds1 x clock . this clock signal is used for three purposes: to generate ds1 ais (all 1s), as a reference to the ds1 dja, and as a cloc k source for the test pattern generator and test pattern monitor. this input may be pr ovided by a 1.544 mhz, a 24.704 mhz, or a 49.408 mhz 32 ppm free-r unning crystal oscillato r or clocking chip. note: for the ds1 dja, an input of 24.704 mhz or 49.408 mhz must be used. e19 ds3xclk i pd ds3 x clock. a 44.736 mhz 20 ppm clock input for ds3 dja and tpg. this input may be provided by a 44.736 mhz 20 ppm free-running crysta l oscillator or clocking chip. h18 e3xclk i pd e3 x clock. a 34.368 mhz 20 ppm clock input for e3 dja and tpg. this input may be provided by a 34.368 mhz 20 ppm free-ru nning crystal oscillato r or clocking chip. table 2-17. low-order path overhead access, transmit direction pin symbol type name/description b22 lopohclkin i pd low-order path overhead clock. 19.44 mhz clock supplied from external circuits that provide the low-order path overhead data. d20 lopohdatain i pd low-order path overhead data. the following parts of the low-order (vt) overhead are presented at this pin: comm unication channel bits (o bits), v5, j2, z6/n2, z7, and k4 byte. e20 lopohvalidin i pd low-order path overhead data input valid. this signal is a mask, which in- dicates the location of the overhead bytes in the lopohdatain. table 2-18. low-order path overhead access, receive direction pin symbol type name/description a21 lopohclkout o low-order path overhead clock. 19.44 mhz clock supplied to external cir- cuits that receive the low-order path overhead data. h19 lopohdataout o low-order path overhead data. line and path rei and rdi, o bits, v5, j2, z6/n2, and z7/k4 byte. a20 lopohvalidout o low-order path overhead data output valid. this signal is a mask, which indicates the location of the ov erhead bytes in the lopohdataout.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 30 30 agere systems inc. table 2-19. clock generator pin symbol type name/description af27 clkin_pll i pd on-chip pll reference input. the clock generator can be used to devise a clock of the appropriate frequency (ds1/e1), synchronized to clkin_pll. af26 cg_pllclkout o plltest mode output. pll clock (1.544 mhz, 2.048 mhz) selected by the device register. ak31, ag30, aj31 mode[2:0]_pll i pd pll input clock mode select bits. the settings of these mode select pins must correspond to the frequency of clkin_pll as shown below. mode[2:0]_pll clkin_pll mode[2:0]_pll clkin_pll 000 reserved 100 16.384 mhz 001 51.840 mhz 101 8.192 mhz 010 26.624 mhz 110 4.096 mhz 011 19.440 mhz 111 2.048 mhz
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 31 table 2-20. microprocessor interface pin symbol type name/description g4 mpclk i microprocessor clock. this clock is required to properly sample address, data, and control signals from the microprocessor in both asynchronous and synchronous modes of operation. d2 mpmode i microprocessor mode. if the microprocessor interface is synchronous, mpmode should be set to 1. if the mi croprocessor interface is asynchro- nous, mpmode should be set to 0. g7 csn i pu chip select. active-low, high-order address signal. chip select must be set low at the beginning of any read or write access and returned high at the end of the cycle. f3 adsn i address strobe. active-low address strobe that indicates the beginning of a read or write access. it is a one mpclk cycle-wide pulse for synchronous mode. in asynchronous mode, it is active for the entire read/write cycle. address bus signals, addr[20 :0], are available to the ultramapper full transport when adsn is low. the address bus should remain valid for the duration of adsn. j6 rwn i read/write. rwn is set high during a read cycle, or set low during a write cycle. j5 dsn i data strobe. for a read cycle, the contents of the internal register will be output on data [15:0]. for a write cyc le, the data [15:0] will be clocked into the internal register. to initiate the start of the read/write operation, dsn must be low during the entire read/write cycle. this signal should only be used for asynchronous mode. n5, p8, m4, l3, j1, n6, m5, l8, k4, m6, h2, l5, l6, g2, f1, k5, j4, j8, g3, h4, k6 addr[20:0] i address [20:0]. addr[20] is the msb and addr[0] is the lsb for address- ing all the internal registers during microprocessor access cycles. all addresses are 21-bit word addresses; therefore, in a typical application, addr[0] of the tmxa84622 device would be connected to address bit 1 of a byte-addressable system address bus. note: the ultramapper full transport is little-endian , i.e., the least significant byte is stored in the lowest address and the most significant byte is stored in the highest address. ca re must be exercised in connection with microprocessors that use big-endian byte ordering. p1, u9, t4, r4, n2, p4, u5, r5, m1, t5, m2, r8, n4, u2, l2, k1 data[15:0] i/o data [15:0]. 16-bit data bus input for write operations and output for read operations. data[15] is the msb, and data[0] is the lsb. u4, r1 par[1:0] i/o data parity. byte-wide parity bits for data. par[1] is the parity for data[15:8], and par[0] is the parity for data[7:0] t3 dtn o data transfer acknowledge. the delay associated with dtn going low de- pends on the ultramapper full transport block being accessed. in asynchro- nous mode, when adsn or dsn is dea sserted, it will drive the dtn signal high. when inactive, csn will drive dtn to be 3-stated. the microprocessor should wait after dtn is deasserted, before starting the next operation. u8 hp_intn o od high-priority and low-priority interrupt. active-low. each functional block contains its individual low-priority interrupt. high-priority interrupts are gener- ated by the tmux and e13 blocks. each interrupt is individually maskable. requires an external 5 k ? pull-up resistor. w1 lp_intn y1 aps_intn o od automatic protection switch interrupt. active-low. see the tmux section in the register description for specific in terrupts. each interrupt is individually maskable. requires an external 5 k ? pull-up resistor.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 32 32 agere systems inc. table 2-21. boundary scan ( ieee ? 1149.1) pin symbol type name/description an22 tck i test clock. this signal provides timing fo r boundary-scan test operations. ap23 tdi i pu test data in. boundary-scan test data input signal, sampled on the rising edge of tck. an23 tms i pu test mode select. controls boundary-scan test operations. tms is sampled on the rising edge of tck. ag26 trst i pu test reset (active-low). this signal provides an asynchronous reset for the boundary-scan tap controller. aj21 tdo o test data out. boundary-scan test data output signal is updated on the fall- ing edge of tck. the tdo output will be high-impedance, except when transmitting test data. table 2-22. general-purpose interface pin symbol type name/description ak18 rstn i pu global hardware reset. active-low. initializes all internal registers to their default state. this is an asynchrono us reset on the fa lling edge, but rstn should be held low for at least 1 s . rstn should be held low until both power supplies (1.5 v and 3.3 v) are st abilized upon powerup. aj24 pmrst i/o pd performance monitor reset. resets error counters. when enabled as an input, it is a 1s square wave that forc es an update of pm counters upon the rising edge. when the pmrst is generated internally from the mpu clock, this pin is an output. al20 ic3staten i pu output enable. when high, output buffers will operate no rmally. when low, all outputs will be forced to a high-impedance stat e. ic3staten should be held low until both power supplies (1.5 v and 3.3 v) are stabilized upon pow- erup. ap24 sck1 i pd scan clock 1. reserved. do not connect. am23 sck2 i pd scan clock 2. reserved. do not connect. aj23 scan_en i pd scan enable. reserved. do not connect. ak20 scanmode i pd serial scan input for testing. reserved. do not connect. al21 iddq i iddq input. this pin must be externally pulled down with a 1 k ? resistor. table 2-23. cdr interface pin symbol type name/description am13 bypass i pd high-speed cdr bypass. reserved. do not connect. ag15 tstphase i pd test phase. reserved. do not connect. al14 ecsel i pd external clock select. reserved. do not connect. ap15 etoggle i pd external toggle. reserved. do not connect. ap16 exdnup i pd external down up. reserved. do not connect. aj13 tstmode i pd test mode. reserved. do not connect. ag7 tstsftld i pd test shift load. reserved. do not connect.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 33 table 2-24. analog power and ground signals pin symbol type name/description ap13 v ssa_cdr1 ? cdr1 ground. isolated ground for the internal cdr1. ag13 v ssa_cdr2 ? cdr2 ground. isolated ground for the internal cdr2. ak15 v ssa_x4pll ? x4pll ground. isolated ground for the internal x4pll. ah31 v ssa_sfpll ? sfpll ground. isolated ground for the internal sfpll. d18 v ssa_ds3pll ? ds3pll ground. isolated ground for the internal ds3pll. a19 v ssa_e3pll ? e3pll ground. isolated ground for the internal e3pll. ap14 v dd15a_cdr1 ? cdr1 power. 1.5 v power supply for the internal cdr1, which is used by the high-speed receive cdr, the prot ection receive cdr, and the three cdrs associated with the mate intercon nect ports. good engineering prac- tice needs to be applied; refer to the evaluation board schematic. al11 v dd15a_cdr2 ? cdr2 power. 1.5 v power supply for the internal cdr2, which is used by the high-speed receive cdr, the prot ection receive cdr, and the three cdrs associated with the mate intercon nect ports. good engineering prac- tice needs to be applied; refer to the evaluation board schematic. am16 v dd15a_x4pll ? x4pll power. 1.5 v power supply for the internal x4pll, which is used for the transmit protection 1 + 1 port. good engineering practice needs to be applied; refer to the evaluation board schematic. c19 v dd15a_ds3pll ? ds3pll power. 1.5 v power supply for the internal ds3pll, which is used by the ds3dja. good engineering practice needs to be applied; refer to the evaluation board schematic. b19 v dd15a_e3pll ? e3pll power. 1.5 v power supply for the internal e3pll, which is used by the e3dja. good engineering practice ne eds to be applied; refer to the eval- uation board schematic. ah30 v dd33a_sfpll ? sfpll power. 3.3 v power supply for the internal sfpll, which is used by the cg block (framer pll). good engineering practice needs to be applied; refer to the evaluation board schematic.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 34 34 agere systems inc. table 2-25. digital power and ground signals pin symbol type name/description j10, j13, j14, j17, j18, j21, j2 2, j25, k9, k17, k18, k26, n9, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n26, p9, p13, p22, p26, r13, r22, t13, t22, u10, u13, u22, u25, u26, v10, v13, v22, v25, v26, w13, w22, y13, y22, aa9, aa13, aa22, aa26, ab9, ab13, ab14, ab15, ab16, ab17, ab18, ab19, ab20, ab21, ab22, ab26 , ae9, ae17, ae18, ae26, af10, af13, af14, af18, af21, af22, af25, ah26, aj26, aj27 v dd15 ? common power signals for 1.5 v v dd . a2, a3, b1, b3, b5, b9, b10, b14, b15, b20, b21, b25, b26, b30, b33, b34, c2, c4, c32, c33, c3 4, d3, d5, d32, d33, d34, e2, e4, e33, e34, j2, j11, j12, j15, j1 6, j19, j20, j23, j24, j33, k2, k33, l9, l26, m9, m26, p2, p33, r2, r9, r26, r33, t9, t26, w9, w26, y2, y9, y26, y33, aa2, aa33, ac9, ac26, ad9, ad26, ae2, ae33, af2, af11, af12, af 15, af16, af19, af20, af23, af24, af33, ak2, ak33, ak34 , al33, al34, am34, an14, an15, an20, an21, an25, an26, an30, an34 v dd33 ? common power signals for 3.3 v v dd . b2, c3, c5, c9, c10, c 14, c15, c20, c21, c25, c26, c30, d4, d31, e3, e31, e32, f30, f31, f32, f33, f34, g32, g33, g34, j3, j32, k3, k32, p3, p14, p15, p16, p17, p18, p19, p20, p21, p32, r3, r14, r15, r16, r1 7, r18, r19, r20, r2 1, r32, t14, t15, t16, t17, t18, t19, t20, t21, u14, u15, u16, u17, u18, u19, u20, u21, v14, v15, v16, v17, v18, v19, v20, v21, w14, w15, w16, w17, w18, w19, w20, w21, y3, y14, y 15, y16, y17, y18, y19, y20, y21, y3 2, aa3, aa14, aa15, aa16, aa17, aa18, aa19, aa20, aa21, aa32, ae3, ae32, af3, af32, ag16, ag19, aj7, aj8, aj9, aj10, aj11, ak3, ak7, ak8, ak9, ak10, ak32, al7, al8, al9, al 10, al32, am4, am14, am15, am20, am21, am25, am26, am30, an3, an5, an7, ap3, ap5, ap7 v ss ? common ground signals. table 2-26. no connects pin symbol type name/description n32, n33, p27, p31, r30, r31, r34, t30, t31, t34, u27, u31, u32, v27, v33, v34, w27, w33, w32, y2 7, y31, y34, ab33, ad27, af29, af30, af31, ag28, ag29, ag31, ah29, ah32, ah33, ah34, aj32, aj30, ak 27, aj34, ak26, al29, an32 no connect nc no connect. these pins are not used in the ultramapper full transport device.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 35 3 operating conditio ns and reliability 3.1 absolute maximum ratings stresses in excess of the absolute ma ximum ratings can cause permanent damage to the device. these are absolute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. ex posure to absolute maximum ratings for extended periods can adversely affect device reliability. 3.2 recommended operating conditions table 3-2 lists the voltages, along with the tolerances, that are required for proper operation of the tmxa84622 device. table 3-2. recommended operating conditions * internal reference voltage is used if umpr_lvds_ ref_sel = 1, or else external voltage is used. 3.3 handling precautions although electrostatic discharge (esd) pr otection circuitry has been designed into this device, proper precautions must be taken to avoid exposure to esd and electrical overstress (e os) during all handling, assembly, and test operations. agere employs both a human-body model (hbm) and a charged-device model (cdm) qualification requirement in order to determine esd-suscept ibility limits and protection design evaluation. esd voltage thresholds are de pendent on the circuit parameters used in each of the models, as defined by jedec?s jesd22-a114 (hbm) and jesd22-c101 (cdm) standards. table 3-1. absolute maximum ratings parameter min max unit supply voltage (v dd33 )?0.54.2v supply voltage (v dd15 )?0.32.0v input voltage: lvcmos lvds ?0.3 ?0.3 5.25 v dd33 + 0.3 v v power dissipation ? ? mw storage temperature range ?65 125 c parameter symbol min typ max unit 3.3 v power supply v dd33 3.14 3.3 3.47 v 1.5 v power supply v dd15 1.4 1.5 1.6 v ground v ss ?0.0 ? v 1.0 v: lvds reference* ref10 ? 1.0 ? v 1.4 v: lvds reference* ref14 ? 1.4 ? v ambient temperature t a ?40 ? 85 c table 3-3. esd tolerance device minimum threshold hbm cdm tmxa84622 2000 v 500 v
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 36 36 agere systems inc. 3.4 thermal parameters (d efinitions and values) system and circuit board level performance depends not only on de vice electrical characteristic s, but also on device thermal characteristics. the therma l characteristics frequently determine the limits of circuit board or system performance, and they can be a major cost adder or cost avoida nce factor. when the die temperature is kept below 125 c, temperature-activated failure mechanisms are minimized. the thermal parameters that agere provides for its packages help the chip and system designer choose the best package for thei r applications, including allowing the syst em designer to thermally design and in- tegrate their systems. it should be noted that all the parameters listed below are affect ed, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja - junction to air thermal resistance ja is a number used to express the thermal performance of a part under jedec standard natural convection conditions. ja is calculated using the following formula: ja = (t j ? t amb ) / p; where p = power jma - junction to moving air thermal resistance jma is effectively identical to ja but represents performance of a part mounted on a jedec four layer board inside a wind tunnel with forced air convection. jma is reported at airflows of 200 lfpm and 500 lfpm (linear feet per minute), which roughly correspond to 1 m/s and 2.5 m/s (respectively). jma is calculated using the following formula: jma = (t j ? t amb ) / p jc - junction to case thermal resistance jc is the thermal resistance from junction to the top of the case. this number is determined by forcing nearly 100% of the heat generated in the die out the top of the package by loweri ng the top case temperature. this is done by placing the top of the package in contact with a copper slug kept at room temperature using a liquid refrigeration unit. jc is calculated using the following formula: jc = (t j ? t c ) / p jb - junction to board thermal resistance jb is the thermal resistance from junction to board. this number is determined by forcing the heat generated in the die out of the package through the leads or balls by lowering the board temperature and insulating the package top. this is done using a special fixture, which keeps the board in contact with a water chilled copper slug around the perimeter of the package while insulating the package top. jb is calculated using the following formula: jb = (t j ? t b ) / p jt - junction temperature to case temperature jt correlates the junction temperature to the case temperature. it is generally used by the customer to infer the junction temperature while the part is operating in their syst em. it is not considered a true thermal resistance. jt is calculated using the following formula: jt = (t j ? t c ) / p table 3-4. thermal parameter values parameter temperature c/watt ja 12.8 jma (1 m/s) 9.5 jma (2.5 m/s) 8 jc 2.5 jb 7.6 jt 1
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 37 3.5 reliability product reliability can be calcul ated as the probability that the product will perform under no rmal operating co nditions for a set period of time. factors infl uencing the reliability of a prod uct cover a range of variables, including design and manufac- turing. the failure rate of a pr oduct is given as the number of units failing per unit time. this failure rate is known as fit, which is as follows: 1 fit = 1 failure/1x10 9 hours. another unit used for failure rate is kn own as mtbf, which is 1/fit. many assump tions are made when calculating the failure rate for a product, such as the average junction temperatur e and activation energy. the as sumptions made for calculating fit and mtbf are shown in table 3-5. moisture sensitivity level ?this is based on ipc/jedec test method j-std- 020 (which lists a means of testing and clas- sifying devices for a certain le vel of moisture sensitivity). 3.6 recommended powerup sequence the ultramapper full transport device requires dual power supplies, a 3.3 v supply for the i/o, and a 1.5 v supply for the core. during powerup, rstn should be held low (holding the device in reset) and ic3staten should be held low (3-stating all output buffers). after the 3.3 v and 1.5 v supplies are stable, mpclk (which affects the device reset) should be applied and must be present for at least two clock cycles before rstn and ic3staten are released. it is then recommended that ic3staten be released concurrent with, or after, the release of rstn. there are no constraints as to which supply (3.3 v or 1.5 v) must come up first, nor does it matter how long it takes the second supply to come up after the first supply. additionally, it is recommended that the trst pi n be held low (or pulsed low) upon startup. 3.7 power consumption the power consumption of the device is ap plication dependent since it is not possibl e to use all the device features simul- taneously. the nominal measured values fo r power per block are shown in table 3-8. table 3-5. reliability data junction temperature fit (per 1x10 9 device hours) mtbf activation energy 55 c 22 4.55 x10 7 hours 0.7ev table 3-6. moisture sensitivity level device level tmxa84622 2a l-tmxa84622 (pb-free) 3 table 3-7. typical power co nsumption by application application conditions typ 1.5 v power typ 3.3 v power total power oc12 to 84 ds1 transport mode tmux, three spemprs, thre e vtmprss, three ds1djas, and three frms 1.60 w 0.50 w 2.1 w oc12 to 6 ds3 clear ch annel tmux, six spemprs, one ds3dja, and six ds3 i/os 1.00 w 0.75 w 1.75 w oc12 to stspp high-speed loopback through stspp and tmux 0.90 w 0.50 w 1.4 w oc12 to 84 ds1 portless trans- mux application, transport mode tmux, three sts1lts, five spemprs, three vtmprs, two m13s, three ds1djas, and three frms 1.70 w 0.85 w 2.55 w oc12 to 84 ds1 transmux application, transport mode tmux, three sts1lts, three spemprs, three vtmprs, three m13s, thr ee ds1djas, and three frms 1.70 w 0.60 w 2.3 w
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 38 38 agere systems inc. testing has shown that, on the average, approxi mately 0.35 w can be saved by utilizing the divide by 16 mpu clock power down feature. please refer to mpu register 0x0019 in the ultramapper register description document for further information. additional mpu clock divisor options are available. additional power can be saved by powering down unused lvds buffers. for details, please see mpu register 0x0026 in the ultramapper register description document. table 3-8. typical power consumption per block typical power by block refers to all instances being used. block maximum instance typical, per single instance unit tmux 1 0.120 w stspp 1 0.020 w stsxc 1 0.200 w mrxc 1 0.050 w spempr 6 0.009 w sts1lt 3 0.028 w vtmpr 3 0.015 w e13 3 0.013 w m13 3 0.013 w tpg/tpm 1 tbd w frm 3 0.195 w ds1dja 3 0.026 w ds3dja 1 0.050 w mpu 1 0.420* w cdr/pll 1 0.150 w lvds i/o 15 0.020 w nsmi i/o 3 0.032 w ds3 i/o 6 0.050 w * measured with a 50 mhz mpclk. with a 25 mhz mpclk, the typi cal per single instance value of mpu power is approximately 0.2 w.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 39 4 electrical characteristics 4.1 lvcmos interface characteristics table 4-1. lvcmos input specifications parameter symbol conditions min typ max unit input leakage current i i v ss < v in < v dd33 ? ? 1.0* a high-input voltage v ih ?2.0??v low-input voltage v il ?v ss ?0.8v input capacitance c i ???1.5pf * excludes current due to pull -up or pull-down resistors. table 4-2. lvcmos output specifications parameter symbol conditions min typ max unit output voltage low v ol i ol = max v ss ?0.5v output voltage high v oh i ol = max v dd ? 0.5 ? v dd v output current low i ol ???6*ma output current high i oh ????6*ma output capacitance c o ??3?pf hiz output leakage current i oz ???10a * output current = 10 ma (maximum) for dtn and nsmitxclk[3:1]. table 4-3. lvcmos bidirectional specifications parameter symbol conditions min typ max unit leakage current i l v ss < v in < v dd33 ?? 11 a high-input voltage v ih ?2.0?v dd33 + 0.3 v low-input voltage v il ?v ss ?0.8v biput capacitance c ib ? ? 5.0 ? pf output voltage low v ol i ol = ?6 ma* ? ? 0.5 v output voltage high v oh i oh = 6 ma* 2.4 ? ? v output current low i ol ???6ma output current high i oh ????6ma * the following bidirectional pins c an sink/source 10 ma: nsmirxclk[3:1].
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 40 40 agere systems inc. 4.2 lvds interface characteristics 3.3 v 5% v dd , ?40 c to +125 c junction temperature. . table 4-4. lvds interface dc characteristics parameter symbol test conditions min typ max unit input buffer parameters input voltage range high (v ia or v ib ) low (v ia or v ib ) v i v ih v il |v gpd | < 925 mv, dc?1 mhz ? 0 ? ? 2.4 ? v v input differential threshold v idth dc? 450 mhz ?100 ? 100 mv input differential hysteresis v hyst (+v idth ) ? (?v idth )???*mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 ? output buffer parameters output voltage: high (v oa or v ob ) low (v oa or v ob ) v oh v ol r load = 100 ? 1% r load = 100 ? 1% ? 0.925 ? ? 1.475 ? v v output differential voltage ? |v od |r load = 100 ? 1% 0.25 ? 0.45 v output offset voltage v os r load = 100 ? 1% 1.125 ? 1.275 v output impedance, single ended r o v cm = 1.0 v and 1.4 v 80 100 120 ? r o mismatch between a and b ? r o v cm = 1.0 v and 1.4 v ? ? 10 % change in differential voltage between complementary states | ? v od |r load = 100 ? 1% ? ? 25 mv change in output offset voltage between complementary states ? v os r load = 100 ? 1% ? ? 25 mv output current i sa , i sb driver shorted to v ss ??24ma output current i sab drivers shorted together ? ? 12 ma * the buffer will not produce output transitions when input is open-circuited. when the true and complement inputs are floating , the input buffer will not oscillate. ? 250 mv |v a ? v b | 450 mv. note: the characteristics in the table above apply under the following conditions: external lvds reference chos en (umpr_lvds_ref_sel = 0). ref10 = 1.0 v 3% and ref14 = 1.4 v 3%. internal lvds reference chosen (umpr_lvds_ref_sel = 1). vdd33 supply controlled to within 3%. when umpr_lvds_ref_sel = 1, the internal reference levels are der ived using a resistor ladder from vdd33. these levels will var y as much as the vdd33 supply does and are therefore only as accurate as the vdd33. if vdd33 cannot be controlled to within 3%, one or more ieee specifications may be violated. while this may not necessarily lead to data e rrors during transmission, inter operability issues may arise due to specification noncompli- ance.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 41 5 timing 5.1 tmux high-speed interface timing figure 5-1. tmux lvds signal rise/fall timing figure 5-2. tmux lvds clock and data timing table 5-1. high-speed interface input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) rhsdp/n (622 mhz) * * input serial data stream should have minimum eye opening of 0. 4 uip-p, and no more than 60 consecutive bits that have no tra nsitional edge within one minute. it must meet 100 ps maximum phase variation li mit over a 200 ns interval; this translates to a frequency cha nge of 500 ppm. asynchronous ? 0.5 0.5 ? ? rhsdp/n (155 mhz) * asynchronous ? 0.5 0.5 ? ? rhsdp/n (155 mhz) rhscp/n r/f 1.0 1.0 2 0 t f t r 80% 20% thscop/n rhscp/n t su t h t pd 50% 50% 50% 50% rhsdp/n thsdp/n
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 42 42 agere systems inc. 5.2 thssync characteristics thssync is an 8 khz composite frame sync pulse for sts-3 or sts-12. thssync contains j 0 , j 1 , and v 1-1 information as shown in figure 5-3. the time delay from any rising edge of a j 0 (8 khz) to the rising edge of the next j 0 is 125 s. the time delay between any two v 1-1 (2 khz) pulses is 500 s. this is tr ue whether in sts-3 or sts-12 mode. when mpu_master_slave = 1, then thssync is according to figure 5-3. figure 5-3. thssync timing di agram (mpu_master_slave = 1) when mpu_master_slave = 0, then thssyn c (supplied from an ex ternal source) can be according to figure 5-4. table 5-2. protection link input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) rpsdp/n (622 mhz) * * input serial data stream should have minimum eye opening of 0. 4 uip-p, and no more than 60 consecutive bits that have no tra nsitional edge within one minute. it must meet 100 ps maximum phase variation li mit over a 200 ns interval; this translates to a frequency cha nge of 500 ppm. asynch ? 0.5 0.5 ? ? rpsdp/n (155 mhz) * asynch ? 0.5 0.5 ? ? rpsdp/n (155 mhz) rpscp/n r 1.0 1.0 2 0 table 5-3. high-speed interface output specifications name reference edge rising/falling propagation delay min (ns) max (ns) thsdp/n (622.08 mhz or 155.52 mhz) thscop/n r 0.3 0.8 thssync (mpu_master_slave = 1) tlsclk ? ?0.5 0.2 table 5-4. protection link output specifications name reference edge rising/falling propagation delay min (ns) max (ns) tpsdp/n (622.08 mhz or 15 5.52 mhz) tpscp/n r 0.3 0.8 sts-3 j 0 j 1-1 j 0 j 1-2 j 1-3 v 1-1 j 1-1 j 1-2 j 1-3 first frame 50 ns second frame third frame fourth frame sts-12 v 1-2 v 1-3 j 0 j 0 j 1-1 j 1-2 j 1-3 j 1-1 j 1-2 j 1-3 v 1-1 v 1-2 v 1-3 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 50 ns j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 1-1 j 1-2 j 1-3 j 1-5 j 1-7 j 1-9 j 1-11 j 1-4 j 1-6 j 1-8 j 1-10 j 1-12 j 0 j 0 j 0 j 0 12.5 ns first frame second frame third frame fourth frame
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 43 figure 5-4. thssync timing di agram (mpu_master_slave = 0) when supplied externally, the 8 khz thssync may have a 50/50 du ty cycle since the signal will only be sampled on the rising edge. in this case, thssync should be synchronous to thsc. although there are no set-up/hold specifications for the thssync input with respect to thsc, thssync still needs to be sy nchronous to the input tr ansmit high-speed clock (thsc). the device looks for t he rising edge of thssync to occu r regularly in each frame wit hin a window, defined by the setting in tmux_sync_offset[3:0]. a cloc k derived from thsc samp les the incoming frame sync. if thssync is not synchronous to thsc, over time, the ri sing edge of thssync will fall outside th e window causing an sts-n/stm-n level lof. however, if the system needs to synchronize vts, generated from different ultramapper full transport devices or other ex- ternal devices, then thssync needs to look like the waveform re presentation in figure 5-5, i.e., thssync must be com- posed of both the 8 khz and the 2 khz sync components (j 0 + v 1-1? v 1-3 ); the j 1 portion is not needed. figure 5-5. thssync timing di agram for synchronized vts figure 5-6 depicts the relationsh ip between the rising edge of the input thssync (when the de vice is in slave mode) and the beginning of the sonet frame output on thsd. the de lay between thssync and the start of the outgoing sonet frame is contributed to internal device delays (pertaining to multiplexing functionality, fifo , and parallel-to-serial conver- sion). figure 5-6. rela tionship between thssync and thsd sts-3 j0 first frame 50 ns sts-12 50 ns 125 s 125 s j0 j0 j0 second frame third frame fourth frame second frame third frame fourth frame first frame j0 j0 j0 j0 sts-3 j 0 j 0 v 1-1 first frame 50 ns second frame third frame fourth frame sts-12 v 1-2 v 1-3 j 0 j 0 v 1-1 v 1-2 v 1-3 50 ns j 0 j 0 j 0 j 0 first frame second frame third frame fourth frame thssync thsd x y a1 note: 622 mbits/s mode: n = 80 8 bits. 155 mbits/s mode: n = 44 8 bits. for the case where tmux_tlbitcnt, tmux_tlstscnt, tmux_tlcolcnt, and tmux_tlrowcnt a ll = 0 (default), changing these register values will change the location of po int x with relation to point y. n
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 44 44 agere systems inc. 5.3 sts-3/stm-1 mate interconnect timing figure 5-7. sts-3/stm-1 mate rise/fall timing figure 5-8. sts-3/stm-1 ma te clock and data timing table 5-5. sts-3/stm-1 mate interconnect input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) tlsdatap/n[3:1] asynchronous ? ???? table 5-6. sts-3/stm-1 mate interconnect output specifications name reference edge rising/falling propagation delay min (ns) max (ns) rlsdatap/n[3:1] asynchronous ? ? ? t f t r 80% 20% clock clock t su t h t pd 50% 50% 50% 50% tlsdatap/n rlsdatap/n
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 45 5.4 toac, poac, and lopoh timing the relationships between data, clock, and sync signals are specific to the toac and poac operation mode selected. this is explained in detail in the toac/poac chapter of the system design guide. note: for information pertaining to the output clock duty cycle (in various toac/poac modes of operation), please refer to table 6-13 an ta b l e 6 - 1 4 . figure 5-9. toac, poac timing note: for all modes, sync signals are high during t he clock period of the fi rst bit of each frame. figure 5-10. lopoh timing table 5-7. toac, poac, and lopoh input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ttoacdata ttoacclk (output) r10103.50 tpoacdata tpoacclk (output) r10103.50 lopohdatain and lopohvalidin lopohclkin f 8 8 5 5 table 5-8. toac, poac, and lopoh output specifications name reference edge rising (r) falling (f) propagation delay min (ns) max (ns) rtoacdata, rtoacsync rtoacclk r 0 3.5 ttoacsync ttoacclk r 0 3.5 rpoacdata, rpoacsync rpoacclk f 0 3.5 tpoacsync tpoacclk r 0 3.5 lopohdataout and lopohvalidout lopohclkout r 0 5 tpoacclk t pd t su t h ttoacclk tpoacdata ttoacdata rpoacdata rtoacdata rpoacclk rtoacclk t su t h lopohclkin lopohdatain lopohdataout t pd lopohclkout
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 46 46 agere systems inc. 5.5 ds3/e3/sts-1 timing figure 5-11 shows a simplified representation of the ds3/e3/sts-1 i/o. figure 5-11. ds3/e3 interface diagram in m13/e13 block table 5-9. ds3/e3 input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ds3posdatain[6:1] ds3negdatain[6:1] ds3datainclk r/f 5 5 3 3 table 5-10. sts-1 input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) ds3posdatain[6:1] ds3negdatain[6:1] ds3datainclk f 5 5 3 3 table 5-11. ds3/e3/sts-1 output specifications name reference edge rising/falling propagation delay min (ns) max (ns) ds3posdataout[6:1] ds3negdataout[6:1] ds3rxclkout r/f 0 3 m13/e13 block demux mux q q clk clk d d ds3datainclk ds3posdatain ds3negdatain ds3dataoutclk ds3posdataout ds3negdataout ds3rxclkout
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 47 5.6 nsmi timing figure 5-12. nsmi clock and data timing for the sts-1 mode figure 5-13. nsmi clock and data diagram for spempr nsmi mode nsmitxclk t pd t su t h nsmirxclk nsmirxdata nsmitxdata nsmi_txdataen (output) nsmi_txclk (51.84 mhz output) sonet frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (51.84 mhz output) sonet frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) position of above pulse is provisionable 0-89 bytes + 0-7 bits before j1 note: tx and rx j1 are not aligned. transmit path pointer is fixed at 522. nsmi_rxdataen (output) 125 s position of above pulse is provisionable 0 - 89 bytes + 0 - 7 bits before j1 125 s separation depends on pointer z3 z3 89 columns z4 toh j1 toh c2 toh z4 z4 89 columns j1 toh c2 toh g1 toh notes: clock from spempr is at 51.84 mhz rate and is not gapped. tx dataen is provided to mark the poh time of the spe. j1 can occur anywhere in the frame and its position is optionally marked by txsync, wh ich is provisioned to be n columns (bytes ) plus m bits earlier in time than j1. during periods where the poh is pres ent, the txdataen signal goes high.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 48 48 agere systems inc. figure 5-14. nsmi clock and data diagram for m13 nsmi mode (nsmi <---> m13 <---> ds3 external i/o) figure 5-15. nsmi clock and data diagram for e13 nsmi mode 1 (nsmi <---> e13 <---> e3 external i/o) nsmi_txdataen nsmi_txclk 44.736 mhz x1 x2 m1 m3 ds3 frame (for info only) x1 nsmi_txdata nsmi_txsync 4760 bits position of this pulse is provisionable 0-256 bits before m1 nsmi_rxclk 44.736 mhz output x1 x2 m1 m3 ds3 frame x1 nsmi_rxdata nsmi_rxsync 4760 bits position of this pulse is provisionable 0-256 bits before m1 nsmi_rxdataen notes: clock from m13 is at 44.736 mhz rate and is not gapped. tx dataen is provided to mark the ds3 frame overhead times. m1 can occur asynchronously and its positio n is optionally marked by t xsync, which is provisioned to be 0 to 255 bits before th e m1 bit. txdataen goes low during ds3 frame overhead bits. nsmi_txdataen (output) nsmi_txclk (34.368 mhz output) e3 frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (34.368 mhz output) e3 frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) nsmi_rxdataen (output) 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data notes: clock from e13 is at 34.368 mhz rate and is not gapped. txdataen is provided to mark the overhead time and control bits time of the e3 frame. c11?s (the first c bit of the first tributar y) position is optionally ma rked by txsync, which is provisioned to be 0 to 255 bit s before c11 (bit 385 of the e3 frame). during periods where the oh is pr esent, the txdataen signal goes low. all c bits are zero and the stuff bits are used for data.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 49 figure 5-16. nsmi clock and data diagram for e13 nsmi mode 2 (nsmi <--> e13 <--> spempr <--> stm-n) table 5-12. nsmi input specifications name reference edge rising/falling max rise time (ns) max fall time (ns) min setup (ns) min hold (ns) nsmirxdata[3:1] nsmirxclk r 3.5 3.5 5 0 nsmirxsync[3:1] nsmirxclk r 3.5 3.5 5 0 nsmirxdata[3:1]* nsmirxclk r 3.5 3.5 3.5 3 nsmirxsync[3:1]* nsmirxclk r 3.5 3.5 3.5 3 * pertinent to ds3 clear channel applicat ion, which uses nsmi i/o?this featur e is available only in v3.0 devices. table 5-13. nsmi output specifications name reference edge rising/falling propagation delay min (ns) max (ns) nsmitxdata[3:1] nsmitxclk r 0.5 8.75 nsmitxsync[3:1] nsmitxclk r 0.5 8.75 rxdataen[3:1] nsmirxclk r 0.5 8.75 txdataen[3:1] nsmitxclk r 0.5 8.75 nsmirxsync[3:1] nsmirxclk r 0.5 8.75 nsmi_txdataen (output) nsmi_txclk (51.84 mhz output) e3 frame (for info only) nsmi_txdata (output) nsmi_txsync (output) nsmi_rxclk (51.84 mhz output) e3 frame (for info only) nsmi_rxdata (input) nsmi_rxsync (output) nsmi_rxdataen (output) 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data 1536 bits position of this pulse is provisionable 0-256 bits before c11 frame, rai, rsvd c11 = 0 cj3 = 0 frame stuff = data notes: clock from e13 is at 51.84 mhz rate and is not gapped. txdat aen is the combination of an internal clock enable and data enable from spempr. txdataen is used to mark the overhead time and control bits time of the e3 frame. clock enable is used to gap the clock rate to 34.368 mhz. c11?s (the first c bit of the first tributar y) position is optionally ma rked by txsync, which is pr ovisioned to be 0 to 255 bit s before c11 (bit 385 of the e3 frame). during periods where the oh is pr esent, the txdataen signal goes low. all c bits are zero and the stuff bits are used for data.
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 50 50 agere systems inc. 5.7 shared low-speed line timing figure 5-17. shared low-speed line clock and data timing table 5-14. shared low-speed line timing input specifications name reference edge rising/falling max rise time max fall time min setup min hold linerxdata[86:1] linerxclk[86:1] r/f 10* (ns) 10* (ns) 15 (ns) 10* (ns) * alternative spec: the maximum rise and fall times may be increased to 20 ns each if the minimum hold time is increased to 12 n s. the minimum setup time will remain at 15 ns. table 5-15. shared low-speed line timing output specifications name reference edge rising/falling propagation delay min (ns) max (ns) linetxdata[86:1] linetxclk[86:1] r/f ?10 10 linetxclk t pd t su t h linerxclk linerxdata linetxdata single-rail shown
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 51 6 reference clocks table 6-1. high-speed interface input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rhscp/n 6.43 155.52 mhz 20 ? 0.4 0.4 nom 45%?55% thscp/n 6.43 155.52 mhz 20 0.01 ui p-p or 64 ps p-p or 0.001 ui rms (12 khz?1.3 mhz) 0.4 0.4 nom 45%?55% thscp/n 1.6 622.08 mhz 20 0.04 ui p-p or 64 ps p-p (12 khz?5 mhz) 0.4 nom 0.6 max ? 45%?55% table 6-2. protection link input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle rpscp/n 6.43 155.52 mhz 20 ? 0.4 0.4 nom 45%?55% table 6-3. ds3/e3/sts-1 input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle ds3dataoutclk[6:1] (ds3 ) 22.353 44.736 mhz 20 0.05 ui p-p or 1.12 ns p-p (10 khz?400 khz) 55max 40%?60% ds3datainclk[6:1] (ds3) 22. 353 44.736 mhz 20 ? 3.5 2.5 max 45%?55% ds3dataoutclk[6:1] (e3) 29.090 34.368 mhz 20 0.03 ui p-p or 0.87 ns p-p (100 khz?800 khz) 55max 40%?60% ds3datainclk[6:1]] (e3) 29. 090 34.368 mhz 20 ? 3.5 2.5 max 45%?55% ds3dataoutclk[6:1] (sts-1) 19.290 51.84 mhz 20 0.01 ui p-p or 0.19 ns p-p or 0.001 ui rms (12 khz?400 khz) 55max 40%?60% ds3datainclk[6:1] (sts-1) 19.290 51.84 mhz 20 ? 3.5 2.5 max 45%?55% table 6-4. ds1/e1 dja i nput clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle e1xclk 15.25 65.536 mhz 50 0.1 ui p-p or 1.5 ns p-p (20 khz?100 khz) 3.5 3.5 max 40%?60% ds1xclk 20.20 49.408 mhz 32 0.1 ui p-p or 2.0 ns p-p (10 khz?40 khz) 3.5 3.5 max 40%?60% e1xclk 30.52 32.768 mhz 50 0.1 ui p-p or 3.0 ns p-p (20 khz?100 khz) 3.5 3.5 max 40%?60% ds1xclk 40.40 24.704 mhz 32 0.1 ui p-p or 4.0 ns p-p (10 khz?40 khz) 3.5 3.5 max 40%?60%
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 52 52 agere systems inc. table 6-5. m13/e13 input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle ds2aisclk 158.42 6.312 mhz 30 ? 5 5 max 45%?55% e2aisclk 118.37 8.448 mhz 30 ? 5 5 max 45%?55% table 6-6. ds3/e3 dja i nput clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle ds3xclk 22.35 44.736 mhz 20 0.01 ui p-p or 0.22 ns p-p (10 khz?400 khz) 3.5 3.5 max 45%?55% e3xclk 29.09 34.368 mhz 20 0.01 ui p-p or 0.29 ns p-p (100 khz?800 khz) 3.5 3.5 max 45%?55% table 6-7. lopoh input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle lopohclkin 51.44 19.44 mhz ? ? 8 8 max 45%?55% table 6-8. microprocessor interf ace input clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle mpclk (min) 62.5 16 mhz ? ? 4 4 min 45%?55% mpclk (max) * 15.0 66.67 mhz ? ? 4 4 max 45%?55% * the following applies to the synchronous microprocessor mode (mpmode pin = 1): if dt n is used, then the maximum frequency for mpclk is determined by the processor?s setup specif ication for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdtnvp d). for example, an 8 ns setup time would limit mpclk to 50 mhz for reliable dtn detection. table 6-9. pll input clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle clkin_pll 19.2 51.84 mhz 20 gr-499 and g.823 ? ? ? 40%?60% table 6-10. high-speed interface output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle thscop/n 6.43 155.52 mhz 20 0.1 uip-p ? ? ? 45%?55% thscop/n 1.6 622 mhz 20 0.1 uip-p ? ? ? 45%?55% table 6-11. protection link output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle tpscp/n 6.43 155.52 mhz 20 ? ? ? ? 45%?55% tpscp/n 1.6 622.08 mhz 20 ? ? ? ? 45%?55%
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 53 table 6-12. line timing interface output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rlsclk 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% tlsclk 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% table 6-13. toac output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rtoacclk (sts1lt; full access) 578 1.728 mhz ? ? 1.5 1.5 nom 40%?60% rtoacclk (tmux; sts-12 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 27%?47%* rtoacclk (tmux; sts-12 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 43%?63%* rtoacclk (tmux; sts-12 full access) 48.22 20.736 mhz ? ? 1.5 1.5 nom 23%?43%* rtoacclk (tmux; sts-3 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 48%?68%* rtoacclk (tmux; sts-3 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 42%?62%* rtoacclk (tmux; sts-3 full access) 192.9 5.184 mhz ? ? 1.5 1.5 nom 23%?43%* ttoacclk (sts1lt; full access) 578 1.728 mhz ? ? 1.5 1.5 nom 40%?60% ttoacclk (tmux; sts-12 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 27%?47%* ttoacclk (tmux; sts-12 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 43%?63%* ttoacclk (tmux; sts-12 full access) 48.22 20.736 mhz ? ? 1.5 1.5 nom 23%?43%* ttoacclk (tmux-sts-3 d1-3 mode) 5.2 ( s) 192 khz ? ? 1.5 1.5 nom 48%?68%* ttoacclk (tmux-sts-3 d4-12 mode) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 42%?62%* ttoacclk (tmux-sts-3 full access) 192.9 5.184 mhz ? ? 1.5 1.5 nom 23%?43%* * positive duty cycle. table 6-14. poac output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/ max duty cycle rpoacclk (tmux) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% rpoacclk (sts1lt) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% rpoacclk (spempr) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (tmux) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (sts1lt) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60% tpoacclk (spempr) 1.73 ( s) 576 khz ? ? 1.5 1.5 nom 40%?60%
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 54 54 agere systems inc. table 6-15. ds3/e3/sts-1 output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle ds3rxclkout [6:1] (ds3) 22.353 44.736 mhz 20 gr-253 1.5 1.5 nom 45%?55% ds3rxclkout [6:1] (e3) 29.09 34.368 mhz 20 g.783 1.5 1.5 nom 45%?55% ds3rxclkout [6:1] (sts-1) 19. 29 51.84 mhz 20 gr-253 1.5 1.5 nom 45%?55% table 6-16. lopoh output clock specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle lopohclkout 51.44 19.44 mhz 20 ? 1.5 1.5 nom 45%?55% table 6-17. pll output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle cg_pllclkout 647.66 1.544 mhz 32 gr-499 ? ? ? 45%?55% cg_pllclkout 488.28 2.048 mhz 50 g.823 ? ? ? 45%?55% table 6-18. shared low-speed receive li ne input/output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle linerxclk (framer; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (framer; e1) 488 .28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (m12) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (e12) 488.28 2 .048 mhz 50 ? 10 10 max 45%?55% linerxclk (vtmpr; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (vtmpr; e1) 488 .28 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (m23) 158.42 6.312 mhz 30 ? 10 10 max 45%?55% linerxclk (e23) 118.37 8 .448 mhz 30 ? 10 10 max 45%?55% linerxclk (dja; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (dja; e1) 488.2 8 2.048 mhz 50 ? 10 10 max 45%?55% linerxclk (tpg; ds1) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linerxclk (tpg; e1) 488.2 8 2.048 mhz 50 ? 10 10 max 45%?55% table 6-19. shared low-speed transmit line input/output clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle linetxclk (framer; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (framer; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (m12) 647.66 1.544 mhz 32 ? 10 10 max 45%?55% linetxclk (e12) 488.28 2.048 mhz 50 ? 10 10 max 45%?55% linetxclk (vtmpr; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (vtmpr; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (m23) 158.42 6.312 mhz 30 ? 10 10 max 45%?55% linetxclk (e23) 118.37 8.448 mhz 30 ? 10 10 max 45%?55% linetxclk (dja; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (dja; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55% linetxclk (tpg; ds1) 647.66 1.544 mhz 32 ? 1.5 1.5 nom 45%?55% linetxclk (tpg; e1) 488.28 2.048 mhz 50 ? 1.5 1.5 nom 45%?55%
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 55 table 6-20. nsmi input/outp ut clocks specifications clock name period (ns) frequency accuracy (ppm) jitter rise (ns) fall (ns) min/max duty cycle nsmirxclk (sts1lt) 19.29 51.840 mhz 20 ? 3.5 3.5 max 45%?55% nsmirxclk (m13) 22.35 44.736 mhz 20 ? 1.5 1.5 nom 45%?55% nsmirxclk (e13) 29.09 34.368 mhz 20 ? 1.5 1.5 nom 45%?55% nsmirxclk (spempr) 19.29 51 .840 mhz 20 ? 3.5 3.5 max 45%?55% nsmitxclk 19.29 51.840 mhz 20 ? 1.5 1.5 nom 45%?55%
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 56 56 agere systems inc. 7 microprocessor interface timing note: to allow proper operation of the micr oprocessor interface upon device/boar d bring up, the recommended powerup sequence (listed in section 3.6 recommended powerup sequence, on page 37 ) should be followed. specifically, to avoid potential bus contention is sues the ic3staten pin should be held low during boot up. 7.1 synchronous write mode the synchronous microprocessor interfac e mode is selected when mpmode (pin d2) = 1. in this mode, mpclk used for the ultramapper full transport is the same as the microprocessor cl ock. interface timing for th e synchronous mode write cycle is given in figure 7-1 and in table 7-1 , and for the read cycle in figure 7-2 and in ta b l e 7 - 2 . notes: mpclk input clock to ultramapper full transport mpu block. addr [20:0] the address will be available throughout the entire cycle. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. adsn must be one mpclk clock period wide. rwn (input) the read (h) write (l) signal is always high except during a write cycle. data[15:0] data will be available during cycle t1. dtn (output) data transfer acknowledge is ac tive-low for one clock and then driven hi gh before entering a high-impedance state. (this is done with an i/o pad using the input as feedback to qual ify the 3-state term.) dtn will become 3-stated when csn is high. typically, dtn is active for four or five mpclk cycles after adsn is low. figure 7-1. microprocessor interface synchronous write cycle?mpmode pin = 1 mpclk addr[20:0] csn adsn rwn data[15:0] dtn (input) t ws t ws t dtnvpd t addrvs t csnvs t ws t 0 t 1 t 2 t 3 t n ? 2 t n ? 1 t n t aipd t apd t apd t apd t apd t dtnipd high z high z t adsnvdtf
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 57 * if dtn is used, then the maximum frequency for mpclk is determined by the processor?s setup specif ication for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdtnvpd). for example, an 8 ns setup time would limit mpclk to 50 mhz for reliable dtn dete ction. ? dtn fall is variable, depending on the bloc k selected for access and in some cases the state of the sonet frame. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exc eed 35 mpclk cycles. certain registers in the vtmpr block ha ve a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vt mpr lower-order path overhead interface as part of sonet overhead termination functions. therefore, the us er must insert long enough delay or use th e dtn signal to read/ write these registers correctly. additiona lly, if the high-speed cdr is used, during initialization, enough time must be provid ed to allow the cdr to stabi- lize. if the cdr has not stabilized, it may take much longer t han 35 mpclk cycles for accesses to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms afte r the cdr has been reset before attempting to access any vtmpr regi s- ters. cdr provisioning is accomp lished via the umpr_clcr register. in addition to the above, the vt_rdy bit must be set before attempting any vtmpr register accesses. table 7-1. microprocessor interface synchronous write cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 * mhz max frequency ? ? ? ? ns t ws adsn, rwn, data (write) valid to mpclk 6.7 ? ? ? ns t apd mpclk to addr, rwn, data, csn (write) invalid ? 0 ? ? ns t csnvs csn valid to mpclk 6 ? ? ? ns t addrvs addr valid to mpclk 3.5 ? ? ? ns t aipd mpclk to adsn invalid ? 0 ? ? ns t dtnvpd mpclk to dtn valid ? ? 2.5 12 ns t dtnipd mpclk to dtn invalid ? ? 2.5 12 ns t adsnvdtf adsn valid to dtn falling ? ? ? ? ? ns
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 58 58 agere systems inc. 7.2 synchronous read mode notes: mpclk input clock to ultramapper full transport mpu block. addr [20:0] the address will be available throughout the entire cycle, and must be stable before adsn turns high. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. adsn must be one mpclk clock period wide. rwn (input) the read (h) write (l) signal is always high during the read cycle. dtn (output) data transfer acknowledge on the host bus interface is in itiated on t6. this signal is active for one clock, and then d riven high before entering a high-impedance state. (this is done wi th an i/o pad using the input as feedbac k to qualify the 3-state term.) dtn wi ll become 3-stated when csn is high. typically, dtn is active four or five mpclk cycles after adsn is low. data [15:0] read data is stable in tn ? 1. the data is guaranteed to be stable no later than the time at which dtn becomes active. figure 7-2. microprocessor interface synchronous read cycle?mpmode pin = 1 * if dtn is used, then the maximum frequency for mpclk is determined by the processor?s setup specif ication for dtn. mpu maximum bus operating frequency = 1/(mpu dtn setup time + tdnvpd). for example, an 8 ns setup time would limit mpclk to 50 mhz for reliable dtn detec tion. ? dtn fall is variable, depending on the bloc k selected for access and in some cases the state of the sonet frame. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exc eed 35 mpclk cycles. certain registers in the vtmpr block ha ve a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vt mpr lower-order path overhead interface as part of sonet overhead termination functions. therefore, the us er must insert long enough delay or use th e dtn signal to read/ write these registers correctly. additiona lly, if the high-speed cdr is used, during initialization, enough time must be provid ed to allow the cdr to stabi- lize. if the cdr has not stabilized, it may take much longer t han 35 mpclk for accesses to certain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms after the cdr has been reset before attempting to access any vtmpr regi sters. cdr provisioning is accomp lished via the umpr_clcr register. in addition to t he above, the vt_rdy bit must be set before attempting any vtmpr regis- ter accesses. table 7-2. microprocessor interface synchronous read cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 * mhz max frequency????ns t avs addr valid to mpclk 3.5 ? ? ? ns t apd mpclk to addr invalid ? 0 ? ? ns t csnsu csn active to mpclk 6 ? ? ? ns t adsnsu adsn valid to mpclk 6 ? ? ? ns t snipd mpclk to adsn inactive ? 0 ? ? ns t dnvpd mpclk to dtn valid ? ? 2.5 12 ns t dnipd mpclk to dtn invalid ? ? 2.5 12 ns t daipd mpclk to data 3-state ? ? 3.5 15 ns t adsnvdtf adsn valid to dtn falling ? ? ? ? ? ns mpclk addr[20:0] csn adsn rwn t adsnsu t snipd t csnsu t avs t 0 t 1 t 2 t n ? 4 t n ? 3 t n ? 2 t n ? 1 t n dtn data[15:0] (output) t daipd t dnvpd t dnipd t adsnvdtf high z high z t apd
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 59 7.3 asynchronous write mode the asynchronous microprocessor interface mode is selected when mpmode (p in d2) = 0. interface timing for the asyn- chronous mode write cycle is given in figure 7-3 and in ta b l e 7 - 3 , and for the read cycle in figure 7-4 and in ta b l e 7 - 4 . although this is an asynchronous in terface, an mpclk is still required. this cloc k can be different (asy nchronous) from the mpu clock. internal to th e chip, rwn, adsn, and dsn will be sampled by mpclk. notes: addr [20:0] address is asynchronously passed from the host bus to the internal bus. the address will be available throughout the entire cycle. addr must be held constant while adsn and dsn are valid (low). csn (input) chip select is an active-low signal. csn must be held low (active) until adsn and dsn are deasserted. adsn (input) address strobe is active-low. adsn must be stable for the entire period. adsn and csn may be connected and driven f rom the same source. dsn (input) data strobe is active-low. data [15:0] write data is asynchronously passed from the host bus to the internal bus. data will be available throughout the ent ire cycle. data must be held constant while dsn is valid (low). rwn (input) the read/write signal should be high for a read cycle and low for a write cycle. it should always be held high, exce pt during a write cycle. rwn must be held low (write) until dsn is deasserted (high). dtn (output) data transfer acknowledge (active-low). dtn is driven ou t of 3-state to inactive-high on the assertion of csn. when the internal transac- tion is complete, dtn goes active-low. dtn is then driven high agai n when either adsn or dsn is deasserted. dtn will become 3-s tated when csn is high. dtn fall is variable, depend ing on the block selected for access and in some cases the state of the sonet fra me. this interval is typically in the 100 ns to 200 ns range, but can be several hundred ns. in lab measurements, it has never exceeded 1000 ns. figure 7-3. microprocessor interface asynchronous write cycle?mpmode pin = 0 addr[20:0] csn adsn dsn rwn data[15:0] dtn (input) t avadsf t dvdsf t csfdtr t dsfdtf t adsrdtr t csrdt3 t dsrdi t dsrrwr t dsnrai t adsrai t aicsr t rwfdsf t avdsf high z high z t csfdsf
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 60 60 agere systems inc. table 7-3. microprocessor interface asynchronous write cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclkmpclk 16 mhz min?66 mhz max frequency????ns t csfdsf csn fall setup and hold to dsn fall 0 ? ? ? ns t aicsr csn rise to addr invalid ? 0 ? ? ns t avadsf addr valid setup and hold to adsn fall 1.0 ? ? ? ns t adsrai adsn rise to addr invalid ? 1.42 ? ? ns t avdsf addr valid setup and hold to dsn fall 0 ? ? ? ns t dsnrai dsn rise to addr invalid ? 0 ? ? ns t rwfdsf rwn fall setup and hold to dsn fall 0 ? ? ? ns t dsrrwr dsn rise to rwn rise ? 0 ? ? ns t dvdsf data valid setup and hold to dsn fall 0 ? ? ? ns t dsrdi dsn rise to data invalid ? 0 ? ? ns t csfdtr csn fall to dtn rise ? ? 5.2 16.0 ns t dsfdtf dsn fall to dtn fall ? 0 ? * ns t adsrdtr adsn or dsn rise to dtn rise ? ? 2.9 13.3 ns t csrdt3 csn rise to dtn 3-state ? ? 2.9 13 ns * certain registers in the vtmpr block have a very long acknowledge cycle (in the order of 32 mpclk cycles). the reason for this is that those registers can also be accessed by the vtmpr lower-order path overhead inte rface as part of sonet overhea d termination functions. therefor e, the user must insert a long enough delay or use the dtn signal to read/write t hese registers correctly. additi onally, if the high-speed cdr i s used, during initialization, enough time must be provided to allow the cdr to stabilize. if the cdr has not stabilized, it may take much longer than 35 mpcl k for accesses to cer- tain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms after the cdr has been reset before attempting to access any vtmpr regi sters. cdr provisioning is accomplished vi a the umpr_clcr register. in addition to th e above, the vt_rdy bit must be set before attempting any vtmpr register accesses.
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 61 7.4 asynchronous read mode notes: addr [20:0] address is asynchronously passed from the host bus to the internal bus. the address will be available throughout the entire cycle. csn (input) chip select is an active-low signal. adsn (input) address strobe is active-low. dsn (input) data strobe is active-low. rwn (input) the read (h) write (l) signal is always high during a read cycle. dtn (output) data transfer acknowledge (active-low). dtn is driven ou t of 3-state to inactive-high on the assertion of csn. when the internal transac- tion is complete, dtn goes active-low. dtn is then driven high agai n when either adsn or dsn is deasserted. dtn will become 3-s tated when csn is high. data [15:0] 16-bit data bus. figure 7-4. microprocessor interface asynchronous read cycle?mpmode pin = 0 addr[20:0] csn adsn dsn dtn data[15:0] t adsrd3 t csrdt3 t adsrdtr t csfdsf rwn t avadsf t avdsf t aicsr t adsrai t dsnrai t dtvdv t dsfdtf t csfdtr high z high z high z high z
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 62 62 agere systems inc. table 7-4. microprocessor interface asynchronous read cycle specifications symbol parameter setup (min) hold (min) delay (min) delay (max) unit mpclk mpclk 16 mhz min?66 mhz max frequency ? ? ? ? ns t csfdsf csn fall setup and hold to dsn fall 0 ? * * csn must be held low (active) until adsn and dsn are deasserted. ??ns t aicsr csn rise to addr invalid ? 0 ? ? ns t avadsf addr valid setup and hold to adsn fall 1.0 ? ? ? addr must be held constant while adsn and dsn are valid (low). ??ns t adsrai adsn rise to addr invalid ? 1.42 ? ? ns t avdsf addr valid setup and hold to dsn fall 0 ? ? ??ns t dsnrai dsn rise to addr invalid ? 0 ? ? ns t csfdtr csn fall to dtn rise ? ? 5.2 16.0 ns t dsfdtf dsn fall to dtn fall ? 0 ? ? ? ? dtn fall is variable, depending on the block selected for access and in some cases, the state of the sonet frame. this inter val is typically in the 100 ns to 200 ns range, but can be several hundred ns. it should never exceed 35 mpclk cycles. certain registers in the vtmpr b lock have a very long acknowledge cycle (in the order of 32 mpclk cycles). t he reason for this is that those registers can also be accessed by the vtmpr lower order path overhead interface as part of sonet overhead te rmination functions. therefore, the user must insert a long eno ugh delay or use the dtn signal to read/write these register s correctly. additionally, if the high-s peed cdr is used, during initialization, eno ugh time must be provided to allow the cdr to stabilize. if the cdr has not stabiliz ed, it may take much longer than 35 mpclk for accesses to ce rtain vtmpr registers (dtn return times on the order of several s). it is recommended that the user wait at least 10 ms after the cdr has been reset before attempting to access any vtmpr registers. cdr provisioning is accomplis hed via the umpr_clcr register. in addition to the above , the vt_rdy bit must be set before attempting any vtmpr register accesses. ns t adsrdtr adsn or dsn rise to dtn rise ? ? 2.9 13.3 ns t csrdt3 csn rise to dtn 3-state ? ? 2.9 13.0 ns t dtvdv dtn valid to data valid ? ? ? 0 ns t adsrd3 adsn rise to data 3-state ? ? 2.9 14 + mpclk data[15:0] is enabled by a retimed version of the adsn. ns
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 63 8 other timing this interface may be used as either synchronous or a synchronous mode. 9 hardware design file references (ibis, spice, bsdl, etc.) available upon request. table 8-1. general-purpose input specifications name reference edge rising/falling rise time (ns) fall time (ns) setup (ns) hold (ns) rstn async ? ? ? ? ? pmrst async ? ? ??? tdi and tms tclk r 5 5 19.5 6.4 table 8-2. miscellaneous output specifications name reference edge rising/falling propagation delay min (ns) max (ns) rhsfsyncn asynchronous ? ? ? table 8-3. general-purpose output specifications name reference edge rising/falling propagation delay min (ns) max (ns) tdo tclk f 12.5 45
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 64 64 agere systems inc. 10 909-pin pbga m1t diagram figure 10-1. ultramapper full transport 909-pin pbga m1t balls and dimensions * * 2 oz option
hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 agere systems inc. 65 11 ordering information table 11-1. ordering information device package comcode TMXA846221BL-21 909-pin pbga m1t 700054130 tmxa846221bl-3 909-pin pbga m1t 700052306 l-tmxa846221bl-3* 909-pin pbgam1t 700077980 * pb-free/rohs
tmxa84622 ultramapper full transport hardware design guide, revision 6 622/155 mbits/s sonet/sdh x ds3/ e3/ds2/ds1/e1 april 5, 2005 66 66 agere systems inc. 12 glossary ais alarm indication signal ami alternate mark inversion aps automatic protection switch asm associated signaling mode ber bit error rate bom bit-oriented message bpv bipolar violation b8zs binary 8 zero code suppression cci common channel signaling cdr clock and data recovery chi concentrated highway interface cmi coded mark inversion crc cyclic redundancy check crv coding rule violation dacs digital access cross-connects dja digital jitter attenuation esf extended superframe exz excessive zeros fcs frame check sequence fdl facility data link feac far-end alarm and control febe far-end block error hdb3 high-density bipolar of order three hdlc high-level data link control liu line interface unit loc loss of clock lof loss of frame los loss of signal lopoh low-order path overhead mcdr mate clock and data recovery mrxc multirate cross-connect nsmi network serial multiplexed interface oof out of frame pbga pin ball grid array poac path overhead access channel prbs pseudorandom bit sequence prm performance report message qrss quasirandom signal source rai remote alarm indicator rdi remote defect indication rpoac receive path overhead access channel rei remote error indication sdh synchronous digital hierarchy sef severely errored frame sonet synchronous optical network tcm tandem connection monitoring toac transport overhead access channels upsr unidirectional path switch ring
agere systems inc. reserves the right to make changes to the pr oduct(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. agere, agere systems, and the agere logo are registered trademarks of agere systems inc. ultramapper is a trademark of agere systems inc. copyright ? 2005 agere systems inc. all rights reserved april 5, 2005 ds02-401bbac-6 (replaces ds02-401bbac-5) for additional information, contact your ager e systems account manager or the following: internet: home: http://www.agere.com sales: http://www.agere.com/sales e-mail: docmaster@agere.com n. america: agere systems inc., lehigh valley central campus, ro om 10a-301c, 1110 american parkway ne, allentown, pa 18109-9138 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: china: (86) 21-54614688 (shanghai), (86) 755-25881122 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 6741-9855 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 1344 296 400 hardware design guide, revision 6 tmxa84622 ultramapper full transport april 5, 2005 622/155 mbits/s so net/sdh x ds3/e3/ds2/ds1/e1 13 change history 13.1 changes to this document since revision 5 on page 31 , eliminated sts1lt from the description. on page 39 , added two rows to table 4-3. starting on page 51, updated the duty cycle in all tables in section 6. other changes that were made to this document (s ince revision 5) are listed below. 13.2 navigating through an adobe acrobat document if the reader displays this document in acrobat reader , clicking on any blue entry in the te xt will bring the re ader to that ref- erence point. ieee is a registered trademark of the institute of electrical and elec tronics engineers, inc. adobe acrobat and acrobat reader are registered trademarks of adobe systems incorporated. table 13-1. document changes change change change change change change page 37 page 43 page 56 page 58 page 64 page 65

▲Up To Search▲

Price & Availability of TMXA846221BL-21

	To Download TMXA846221BL-21 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .